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US 7,120,842 B2Granted
Mechanism to enhance observability of integrated circuit failures during burn-in tests
AssigneeTexas Instruments Incorporated
InventorsGordhan Barevadia, Anupama Aniruddha Agashe, Nikila Krishnamoorthy, Rubin Ajit Parekhji, Neil J. Simpson
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Abstract
A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are monitored during the burn-in tests to provide a mechanism for observing selective scan chain outputs and memory BIST status outputs.
Claims15
A test system comprising:
- a burn-in configuration register;
- combinational logic operational in response to IC Die identification (ID) scan data and burn-in configuration register data to generate Die ID scan out signals;
- means for generating memory built-in self-test (BIST) signals;
- means for generating scan chain signals;
- and
- exclusive-OR logic operational in response to the Die ID scan out signals, memory BIST signals, and scan chain signals to generate monitored output signals.
3 more elements
A test system comprising:
- means for configuring the test system;
- means for generating Die identification (ID) scan out signals;
- means for generating memory built-in self-test (BIST) signals;
- means for generating scan chain signals;
- and
- exclusive-OR logic operational in response to the Die ID scan out signals, memory BIST signals, and scan chain signals to generate monitored output signals.
3 more elements
A method of testing integrated circuit failures on a test system comprising:
- configuring test system;
- generating Die identification (ID) scan out signals;
- generating memory built-in self-test (BIST) signals;
- generating scan chain signals;
- and
- generating monitored output signals, wherein the monitored output signals are generated using exclusive-OR logic operation in response to the Die ID scan out signals, memory BIST signals, and scan chain signals.
3 more elements
Dependencies are inferred from the claim text.