System and method for aligning signals in multiple clock systems

A method for aligning an input signal synchronized to a first clock signal with a second clock signal including the steps of:

• generating a third clock signal that is a phase shifted version of said second clock signal;
• loading said input signal into memory in accordance with said third clock signal;
• and
• reading said input signal from said memory in accordance with said second clock signal.

A system for aligning an input signal synchronized to a data-capture clock signal with a signal-processing clock signal comprising:

• a control module adapted to receive said signal-processing clock signal and generate a data-transit clock signal, which is a phase shifted version of said signal-processing clock signal;
• a first register adapted to receive said data-transit clock signal and in accordance therewith load said input signal;
• and
• a second register adapted to receive said signal-processing clock signal and in accordance therewith load said input signal from said first register.