Instruction-initiated power management method for a pipelined data processor

A method for processing electronic data, comprising:

• receiving at least a plurality of incoming instructions, including a power management instruction, from at least one signal source;
• selectively operating, in response to a first clock signal having active and inactive states, on one or more of said plurality of incoming instructions for data processing by
• generating one or more decoded instructions and one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to said power management instruction by performing, with a first portion of pipeline subcircuitry included in a plurality of subcircuits in response to said active first clock signal, at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of said one or more of said plurality of incoming instructions, and
• executing, with a second portion of said pipeline subcircuitry in response to said active first clock signal, said one or more decoded instructions;
• generating, in response to said one or more local control signals, one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to said one or more first selected assertion and de-assertion states of said one or more local control signals;
• and
• generating, in response to said one or more clock control signals, at least said first clock signal with said first clock signal inactive state corresponding to said one or more second selected assertion and de-assertion states of said one or more clock control signals and following reception of said power management instruction.

A method for processing electronic data, comprising:

• receiving at least a plurality of incoming instructions, including a power management instruction, from at least one signal source;
• selectively operating, in response to a first clock signal having an active state with a plurality of successive cycles and an inactive state with substantially zero cycles, on one or more of said plurality of incoming instructions for data processing by
• generating one or more decoded instructions and one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to said power management instruction by performing, with a first portion of pipeline subcircuitry included in a plurality of subcircuits in response to at least a first one of said plurality of first clock signal cycles, at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of said one or more of said plurality of incoming instructions, and
• executing, with a second portion of said pipeline subcircuitry in response to at least a second one subsequent to said first one of said plurality of first clock signal cycles, said one or more decoded instructions;
• generating, in response to said one or more local control signals, one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to said one or more first selected assertion and de-assertion states of said one or more local control signals with said second selected assertion and de-assertion states following reception of said power management instruction;
• and
• generating, in response to said one or more clock control signals, at least said first clock signal with said first clock signal inactive state corresponding to said one or more second selected assertion and de-assertion states of said one or more clock control signals.

A method for processing electronic data, comprising:

• receiving at least a plurality of incoming instructions, including a power management instruction, from at least one signal source;
• selectively operating, in response to a first clock signal having an active state with a plurality of successive cycles and an inactive state with substantially zero cycles, on one or more of said plurality of incoming instructions for data processing by
• generating one or more decoded instructions and one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to said power management instruction by performing, with a first portion of pipeline subcircuitry included in a plurality of subcircuits in response to at least a first one of said plurality of first clock signal cycles, at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of said one or more of said plurality of incoming instructions, and
• executing, with a second portion of said pipeline subcircuitry in response to at least a second one subsequent to said first one of said plurality of first clock signal cycles, said one or more decoded instructions;
• generating, in response to said one or more local control signals, one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to said one or more first selected assertion and de-assertion states of said one or more local control signals;
• and
• generating, in response to said one or more clock control signals, at least said first clock signal with said first clock signal inactive state corresponding to said one or more second selected assertion and de-assertion states of said one or more clock control signals and following reception of said power management instruction.

A method for processing electronic data, comprising:

• receiving at least a plurality of incoming instructions, including a power management instruction, from at least one signal source;
• selectively operating, in response to a first clock signal having active and inactive states, on one or more of said plurality of incoming instructions for data processing by
• generating one or more decoded instructions and one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to said power management instruction by performing, with a first portion of pipeline subcircuitry included in a plurality of subcircuits in response to said active first clock signal, at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of said one or more of said plurality of incoming instructions, and
• executing, with a second portion of said pipeline subcircuitry in response to said active first clock signal, said one or more decoded instructions;
• generating, in response to said first clock signal, a second clock signal and said one or more local control signals, one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to said one or more first selected assertion and de-assertion states of said one or more local control signals with said second selected assertion and de-assertion states following reception of said power management instruction;
• and
• generating, in response to said one or more clock control signals, said first and second clock signals with said first clock signal inactive state corresponding to said one or more second selected assertion and de-assertion states of said one or more clock control signals and said second clock signal having active and inactive states substantially independent of said one or more second selected assertion and de-assertion states of said one or more clock control signals.

A method for processing electronic data, comprising:

• receiving at least a plurality of incoming instructions, including a power management instruction, from at least one signal source;
• selectively operating, in response to a first clock signal having active and inactive states, on one or more of said plurality of incoming instructions for data processing by
• generating one or more decoded instructions and one or more local control signals having one or more respective assertion and de-assertion states including one or more first selected assertion and de-assertion states corresponding to said power management instruction by performing, with a first portion of pipeline subcircuitry included in a plurality of subcircuits in response to said active first clock signal, at least one or more respective portions of one or more processing, including decoding, operations upon at least one or more respective portions of said one or more of said plurality of incoming instructions, and
• executing, with a second portion of said pipeline subcircuitry in response to said active first clock signal, said one or more decoded instructions;
• generating, in response to said first clock signal, a second clock signal and said one or more local control signals, one or more clock control signals having one or more respective assertion and de-assertion states including one or more second selected assertion and de-assertion states corresponding to said one or more first selected assertion and de-assertion states of said one or more local control signals;
• and
• generating, in response to said one or more clock control signals, said first and second clock signals with said first clock signal inactive state corresponding to said one or more second selected assertion and de-assertion states of said one or more clock control signals and following reception of said power management instruction, and with said second clock signal having active and inactive states substantially independent of said one or more second selected assertion and de-assertion states of said one or more clock control signals.