US 7,120,784 B2 · Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment

Abstract

Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.

Claims28

Dependent claims

In a processor that performs simultaneous multi-threading (SMT) and which includes branch processing logic that has at least one branch history table (BHT) and a predicted target address cache (count cache), a method for improving branch prediction within an SMT environment wit a first thread and a second thread sharing similar lower order addresses, the method comprising:

updating said BHT and said count cache as unified arrays when said first thread and said second thread share a same code;
and
dynamically allocating a first contiguous half of said BHT and of said count cache to said first thread and a second contiguous half of said BHT and said count cache to said second thread, wherein the dynamically allocating to different contiguous halves is triggered only when said first tread and said second thread do not share the same code and wherein the BHT and count cache resume being updated as unified arrays when a next executed pair of threads shares the same code.

In a processor that performs simultaneous multi-threading (SMT) and which includes branch processing logic that has at least one branch history table (BHT) and a predicted target address cache (count cache), a system for improving branch prediction within an SMT environment wit a first thread and a second thread sharing similar lower order addresses, the system comprising:

means for updating said BHT and said count cache as unified arrays when said first thread and said second tread share code;
and
means for dynamically allocating a first contiguous half of said BHT and of said count cache to said first thread and a second contiguous half of said BHT and said count cache to said second thread, wherein the dynamically allocating to different contiguous halves is triggered only when said first thread and said second thread do not share the same code and wherein the BHT and count cache resume being updated as unified arrays when a next executed pair of threads shares the same code.

A data processing system tat provides thread-specific branch prediction in a simultaneous multithreading (SMT) processing environment having a first thread and a second thread, said processing system comprising:

an SMT processor that includes at least one branch history table (BHTs) and a predicted target address cache (count cache), for respectively tracking predictions and target addresses generated for branch prediction mechanism;
a memory coupled to said processor and from which code for said first and said second thread is retrieved by said SMT processor;
means for coupling said memory to said processor;
and
means, within said SMT processor for:
tracking predictions and targets of the first thread and the second thread in a unified view of the BHT and the count cache whenever the first thread and second thread shares the same code;
dynamically splitting an indexed array of said BHT and of said count cache into two logically separate partitions for individually tracking predictions and targets of said first thread and said second thread in separate partitions when the first thread and the second thread do not share the same code, such that more accurate prediction is achieved;
and
dynamically returning to tracking a next pair of threads executing on the processor via the united view of the BHT and the count cache when the next pair of threads shares the same code.

6 more elements

Dependencies are inferred from the claim text.

Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment

Life of this patent

Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment

Life of this patent

Abstract

Claims28