Address offset generation within a data processing system

A method of processing data, said method comprising the steps of:

• controlling data processing operations using an instruction decoder responsive to program instructions;
• and
• generating an N-bit address offset having a value specified by an address offset generating instruction including an offset value sign specifying bit S using an address offset generating circuit controlled by said instruction decoder;
• wherein
• said N-bit address offset has bit values Bi when expressed as a two's complement number, where (N−1)≧i≧Z and (N−1)>Z≧0, said address offset generating instruction includes L high order field bits Pk, where (N−Z)>L≧1 and L>k≧0, and said address offset generating circuit is operable such that:
• (i) if all of said high order field bits Pk have respective predetermined values Dk, then bits Bj of said N-bit address offset are given by Bj=S for all values of j such that (N−1)≧j≧(N−L−1);
• and
• (ii) if any of said high order field bits Pk does not have said predetermined value Dk, then bits Bj of said N-bit address offset, where (N−1)≧j≧(N−L−1), are given by a predetermined one-to-one mapping from combinations of values of said high order field bits Pk and said offset value sign specifying bit S to combinations of values of Bj other than the combination Bj=1 for all values of j such that (N−1)≧j≧(N−L−1) and the combination Bj=0 for all values of j such that (N−1)≧j≧(N−L−1).

A computer product comprising a computer readable storage medium containing computer readable instructions that when executed are for controlling a computer to perform the steps of:

• controlling data processing operations using an instruction decoder responsive to program instructions;
• and
• generating an N-bit address offset having a value specified by an address offset generating instruction including an offset value sign specifying bit S using an address offset generating circuit controlled by said instruction decoder;
• wherein
• said N-bit address offset has bit values Bi when expressed as a two's complement number, where (N−1)≧i≧Z and (N−1)>Z≧0, said address offset generating instruction includes L high order field bits Pk, where (N−Z)>L≧1 and L>k≧0, and said address offset generating circuit is operable such that:
• (i) if all of said high order field bits Pk have respective predetermined values Dk, then bits Bj of said N-bit address offset are given by Bj=S for all values of j such that (N−1)≧j≧(N−L−1);
• and
• (ii) if any of said high order field bits Pk does not have said predetermined value Dk, then bits Bj of said N-bit address offset, where (N−1)≧j≧(N−L−1), are given by a predetermined one-to-one mapping from combinations of values of said high order field bits Pk and said offset value sign specifying bit S to combinations of values of Bj other than the combination Bj=1 for all values of j such that (N−1)≧j≧(N−L−1) and the combination Bj=0 for all values of j such that (N−1)≧j≧(N−L−1).