Inter-procedural allocation of stacked registers for a processor
AssigneeIntel Corporation
InventorsYang Liu, Sun Chan, Guangrong Gao, Dz-Ching (Roy) Ju, Guei-Yuan Lueh, Zhaoqing Zhang
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Abstract
A method for an allocation of stacked registers for Intel's Itanium® processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.
Claims30
A method of processor stacked register allocation comprising:
- determining stacked register usage characteristics of each procedure of a program having a plurality of procedures, wherein any stacked register overflow caused by the program is automatically managed by a stacked register engine;
- determining a stacked register usage quota for each procedure responsive to the determined stacked register usage characteristics of each procedure relative to at least the stacked register usage characteristics of other procedures of the plurality of procedures;
- and
- allocating stacked register usage to each procedure responsive to the stacked register usage quota of each procedure.
A method of stacked register allocation comprising:
- performing an intra-procedural stacked register allocation analysis of a plurality of procedures of a program, wherein any stacked register overflow caused by the program is automatically managed by a stacked register engine;
- performing an inter-procedural stacked register allocation quota analysis for the plurality of procedures responsive to the intra-procedural stacked register allocation analysis;
- and
- allocating stacked register usage to each procedure of the plurality of procedures responsive to the intra-procedural stacked register allocation quota analysis.
A computer system comprising:
- a processor having a plurality of stacked registers;
- a memory adapted to communicate with the stacked registers;
- a stacked register engine implemented on the processor and adapted to automatically manage spill of the stacked registers to the memory and load from the memory to the stacked registers;
- and
- a stacked register allocation algorithm executed in the processor and adapted to allocate stacked register usage to each procedure of a plurality of procedures in a program.
An article comprising a tangible machine-accessible medium having stored thereon instructions that, when executed by a machine, cause the machine to:
- determine stacked register usage characteristics of stacked registers of a processor by each procedure of a plurality of procedures of a program;
- determine a stacked register usage quota for each procedure responsive to the determined stacked register usage characteristics of each procedure relative to at least the stacked register usage characteristics of other procedures of the plurality of procedures;
- and
- allocate stacked register usage to each procedure responsive to the stacked register usage quota of each procedure.
Dependencies are inferred from the claim text.