Memory transaction ordering
AssigneeIntel Corporation
InventorsJames M. Dodd, David Puffer
Life of this patent
Estimating the term…
Abstract
Machine-readable media, methods, and apparatus are described which order memory transactions to increase utilization of multiple memory channels. In some embodiments, a processor may determine an issue order for memory transactions based on the memory channels that are to service the memory transactions. In some embodiments, the processor attempts to obtain an issue order that minimizes or reduces the number of idle periods experienced by the memory channels. Further, the processor may issue the memory transactions to an external memory controller for servicing in the determined issue order.
Claims24
A method comprising
- generating in a processor a plurality of memory transactions in response to executing software instructions from a memory,
- determining, in the processor, for each memory transaction of the plurality of memory transactions which memory channel of a plurality of memory channels is to service the memory transaction, and
- issuing, from the processor, the plurality of memory transactions to a memory controller in an issue order that is based upon the determined memory channels for the plurality of memory transactions.
For use with a memory controller coupled to memory via a plurality of memory channels, a processor comprising
- core logic to execute instructions read from a memory and to generate a plurality of memory transaction in a transaction order in response to executing the instructions,
- ordering logic to determine an issue order for the plurality of memory transactions that is based upon which memory channel is to service each memory transaction of the plurality of memory transactions, and
- a bus interface to issue the plurality of memory transactions to the memory controller in the issue order.
A system comprising
- a random access memory,
- a memory controller coupled to the random access memory via at least two memory channels, and
- a processor comprising
- core logic to generate a plurality of memory transaction in a transaction order in response to executing instructions of the random access memory,
- an ordering unit to determine which memory channel of the at least two memory channels is to service each memory transaction of a plurality of memory transactions and to determine an issue order for the plurality of memory transactions that is based upon the determined memory channel for each memory transaction, and
- a bus interface coupled to the memory controller via a bus external to the processor, the bus interface to issue the plurality of memory transactions to the memory controller in the issue order.
A tangible machine-readable medium comprising a plurality of instructions stored therein that in response to being executed by a processor, result in the processor:
- determining a target memory channel for each memory transaction of a plurality of memory transactions that have a transaction order, and
- determining an issue order for the plurality of memory transactions based upon the target memory channel determined for each memory transaction of the plurality of memory transactions.
Dependencies are inferred from the claim text.