Method and related apparatus for controlling data transmission in a memory
AssigneeVIA Technologies, Inc.
InventorsEric Chuang, Macalas Yen
Life of this patent
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Abstract
A computer system has a processor, a memory for storing data, and a memory controller electrically connected to the processor and the memory for controlling data transmission with the memory. The method includes driving the memory controller to retrieve a data bit located in a first memory address, and driving the memory controller to store the data bit in the a second memory address without delivering the data bit to the processor.
Claims18
A method of controlling data transmission within a memory of a computer system, the computer system comprising a processor, and a memory controller connected to the processor and the memory, the method comprising the following steps:
- delivering a plurality of data located in a plurality of first memory addresses of the memory to the memory controller;
- the memory controller directly storing the plurality of data in a plurality of second memory addresses of the memory instead of transmitting the plurality of data to the processor:
- and
- if the first memory addresses are continuous, delivering a source memory address and a bit length of the plurality of data to the memory controller.
A computer system comprising:
- a processor for controlling operations of the computer system;
- a memory comprising a plurality of first memory addresses and a plurality of second memory addresses;
- and
- a memory controller electrically connected to the processor and the memory, the memory controller having an internal data transmission controller for retrieving a plurality of data according to the first memory addresses, and directly storing the plurality of data in the second memory addresses instead of transmitting the plurality data to the processor;
- wherein if the first memory addresses are continuous, a source memory address and a bit length of the plurality of data are delivered to the memory controller and at least a target memory address is provided so that the memory controller directly stores the plurality of data in the second memory addresses.
Dependencies are inferred from the claim text.