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US 7,120,761 B2Granted
Multi-port memory based on DRAM core
AssigneeFujitsu Limited
InventorsYasurou Matsuzaki, Takaaki Suzuki, Masafumi Yamazaki, Kenichi Kawasaki, Shinnosuke Kamata, Ayako Sato, Masato Matsumiya
Life of this patent
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Abstract
A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
Claims41
A semiconductor memory device, comprising:
- a plurality of N external ports, each of which receives commands, wherein N a command inputs into the N respective external ports are independent of each other, and specify types of respective access operations;
- and
- an internal circuit which performs at least N access operations corresponding to the N command inputs during a minimum interval of two consecutive commands that are input into one of the external ports.
A semiconductor memory device, comprising:
- a memory array;
- N (N is an integer more than one) external ports, each of which receives first commands, wherein N command inputs into the N respective external ports are independent of each other and specify types of internal operations;
- an internal command generating circuit which internally and independently generates a second command,
- wherein a minimum input cycle of two consecutive commands received by each of the external ports is set equal to or more than a period in which said semiconductor memory device performs N+1 internal operations including internal operations corresponding to the N command inputs.
1 more element
A semiconductor memory device, comprising:
- a memory array;
- N (N is an integer more than one) external ports, each of which receives first commands;
- an internal command generating circuit which internally and independently generates a second command,
- wherein a minimum input cycle of the first commands received by each of the external ports is set such that said semiconductor memory device
- performs at least n internal operations within m (m>=2) times the minimum input cycle where mN<n<m(N+1).
2 more elements
Dependencies are inferred from the claim text.