Harvard architecture microprocessor having a linear addressable space
AssigneeSTMicroelectronics S.r.l.
InventorsFranck Roche, Didier Cavalli
Life of this patent
Estimating the term…
Abstract
A microprocessor is connected to a first memory space through a first bus and to a second memory space through a second bus. The microprocessor includes a processing unit that includes a program bus and a data bus, and an interface unit connected, on one side, to the program bus and to the data bus and, on the other side, to the first and second buses. The interface includes a switching circuit for connecting the program bus and the data bus, respectively, to either the first bus or the second bus, in accordance with respective requests for accessing the program and data sent by the processing unit.
Claims23
A microprocessor to be connected to a first memory through a first bus and to a second memory through a second bus, the microprocessor comprising:
- a processing unit;
- a program access bus connected to said processing unit;
- a data access bus connected to said processing unit;
- a bus interface unit connected to the first and second buses, to said program instruction access bus and to said data access bus, said bus interface unit comprising
- a first switching circuit for connecting said program access bus to either the first bus or the second bus in accordance with a program access request sent by said processing unit, and
- a second switching circuit for connecting said data access bus to either the first bus or the second bus in accordance with a data access request sent by said processing unit;
- and
- an access control circuit for arbitrating accessing contention occurring when said processing unit simultaneously sends the data access request and the program access request relating to a same memory space.
A microprocessor system comprising:
- a first memory and a first bus connected thereto;
- a second memory and a second bus connected thereto;
- and
- a microprocessor connected to said first and second memories via said first and second buses, respectively, said microprocessor comprising
- a processing unit,
- a program access bus connected to said processing unit,
- a data access bus connected to said processing unit, and
- a bus interface unit connected to said first and second buses, to said program access bus and to said data access bus, said bus interface unit comprising
- a first switching circuit for connecting said program access bus to either the first bus or the second bus in accordance with a program access request sent by said processing unit,
- a second switching circuit for connecting said data access bus to either the first bus or the second bus in accordance with a data access request sent by said processing unit, and
- an access control circuit for arbitrating accessing contention occurring when said processing unit simultaneously sends the data access request and the program access request relating to a same memory space.
A method for accessing an instruction code stored in a first memory and a data element stored in a second memory using a microprocessor, with the first and second memories being connected to the microprocessor via first and second buses, respectively, and the microprocessor comprises an executable program instruction access bus connected to a processing unit, a data access bus connected to the processing unit, and a bus interface unit connected to the first and second buses, to the program access bus and to the data access bus, the method comprising:
- connecting the program access bus to either the first bus or the second bus in accordance with a program access request sent by the processing unit;
- connecting the data access bus to either the first bus or the second bus in accordance with a data access request sent by the processing unit;
- and
- arbitrating accessing contention occurring when the processing unit simultaneously sends the data access request and the program access request relating to a same memory space.
Dependencies are inferred from the claim text.