Back to results
US 7,120,755 B2Granted
Transfer of cache lines on-chip between processing cores in a multi-core system
AssigneeIntel Corporation
InventorsSujat Jamil, Quinn W. Merrell, Cameron B. McNairy
Life of this patent
Estimating the term…
Abstract
Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific embodiments are described, using write buffers, fill buffers, and multiplexers, respectively, to achieve the on-chip transfer of data between dedicated caches.
Claims13
An apparatus, comprising:
- an integrated circuit including:
- a first processor with a first dedicated cache;
- a second processor with a second dedicated cache;
- and
- control logic, coupled to the first and second dedicated caches, having:
- a first multiplexer coupled to the first and second caches to receive a first cache line from the first dedicated cache and to provide the first cache line to the second dedicated cache;
- and
- a second multiplexer coupled to the first and second caches to receive a second cache line from the second dedicated cache and to provide the second cache line to the first dedicated cache.
5 more elements
An apparatus, comprising:
- an integrated circuit including:
- a first processor with a first dedicated cache;
- a second processor with a second dedicated cache;
- and
- control logic, coupled to the first and second dedicated caches, having:
- a first fill buffer coupled to the first and second dedicated caches to receive a first cache line from the first dedicated cache and to provide the first cache line to the second dedicated cache;
- and
- a second fill buffer coupled to the first and second dedicated caches to receive a second cache line from the second dedicated cache and to provide the second cache line to the first dedicated cache.
5 more elements
A method, comprising:
- transferring a first cache line directly from a first dedicated cache of a chip multi-processor to a first multiplexer within control logic coupled to the first cache in the chip multi-processor;
- subsequently transferring the first cache line from the first multiplexer directly to a second dedicated cache of the chip multi-processor,
- transferring a second cache line directly from the second dedicated cache to a second multiplexer within the control logic coupled to the second cache in the chip multi-processor;
- and
- subsequently transferring the second cache line from the second multiplexer directly to the first dedicated cache.
2 more elements
A method, comprising:
- transferring a first cache line directly from a first dedicated cache of a chip multi-processor to a first write buffer within control logic coupled to the first cache in the chip multi-processor;
- subsequently transferring the first cache line from the first write buffer directly to a second dedicated cache of the chip multi-processor,
- transferring a second cache line directly from the second dedicated cache to a second write buffer within the control logic coupled to the second cache in the chip multi-processor;
- and
- subsequently transferring the second cache line from the second write buffer directly to the first dedicated cache.
2 more elements
A system, comprising:
- a main memory,
- a chip multiprocessor coupled to the main memory and including:
- a first processor with a first dedicated cache;
- a second processor with a second dedicated cache;
- and
- control logic, coupled to the first and second dedicated caches, having:
- a first multiplexer coupled to the first and second caches to receive a first cache line from the first dedicated cache and to provide the first cache line to the second dedicated cache;
- and
- a second multiplexer coupled to the first and second caches to receive a second cache line from the second dedicated cache and to provide the second cache line to the first dedicated cache.
6 more elements
Dependencies are inferred from the claim text.