Synchronous DRAM with selectable internal prefetch size
AssigneeMicron Technology, Inc.
InventorsKevin J. Ryan, Christopher S. Johnson
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Abstract
A synchronous memory device and its method of operation which can be set to operate at a plurality of supported prefetch modes. The prefetch mode may be set by programming a portion of a mode register of the memory device or by setting one or more programmable elements. For read operations, the synchronous memory device internally reads data corresponding to the largest supported prefetch size, and outputs read data corresponding to the current mode. For write operations the synchronous memory accepts write data corresponding to the selected prefetch mode and writes the received data to the array. Data words corresponding to data not received are masked from writing via a write masking circuit.
Claims35
A method of operating a memory device supporting a data transfer operation in a plurality of prefetch modes, said method comprising the steps of:
- detecting a current prefetch mode from a reprogrammable element of said memory device;
- if the current prefetch mode corresponds to a first prefetch mode, transferring without masking, a first plurality of words between said memory device and an external device at a rate of one word per data transfer period;
- and
- if the current prefetch mode corresponds to a second prefetch mode, transferring while masking a second plurality of words between said memory device and an external device at a rate of one word per data transfer period;
- wherein said second plurality is less than said first plurality.
A method of operating a memory device supporting a data transfer operation in a plurality of prefetch modes, said method comprising the steps of:
- selecting a first one of the plurality of prefetch modes for storage in a portion of said memory device;
- detecting a current prefetch mode by determining a stored content of said portion of said memory device;
- if the current prefetch mode corresponds to a first prefetch mode, transferring without masking, a first plurality of words between said memory device and an external device at a rate of one word per data transfer period;
- and
- if the current prefetch mode corresponds to a second prefetch mode, transferring while masking a second plurality of words between said memory device and an external device at a rate of one word per data transfer period;
- wherein said second plurality is less than said first plurality.
A memory device comprising:
- a memory array;
- a data transfer circuit for performing a read operation by transferring a plurality of words from the memory array to an external device and for performing a write operation by transferring at least some of said plurality of words from the external device to the memory array;
- and
- a reprogrammable element for storing one of a plurality of prefetch modes;
- wherein said data transfer circuit transfers data between the memory device and an external device at a rate of one word per data transfer period, and operates in accordance with the prefetch mode stored in said reprogrammable element, the plurality of prefetch modes including, at least, a first prefetch mode to transfer a first number of words without masking, and a second prefetch mode to transfer a second number of words by masking at least one of said first number of words, said second number being less than said first number.
A system comprising:
- a processor;
- and
- a memory coupled to said processor, wherein said memory further comprises:
- a memory array,
- a data transfer circuit for performing a read operation by transferring a plurality of words from the memory array to an external device and for performing a write operation by transferring at least some of said plurality of words from the external device to the memory array, and
- a reprogrammable element for storing one of a plurality of prefetch modes;
- wherein said data transfer circuit transfers data between the memory device and an external device at a rate of one word per data transfer period, and operates in accordance with the prefetch mode stored in said reprogrammable element, the plurality of prefetch modes including, at least, a first prefetch mode to transfer a first number of words without masking, and a second prefetch mode to transfer a second number of words by masking at least one of said first number of words, said second number being less than said first number.
Dependencies are inferred from the claim text.