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US 7,120,749 B2Granted
Cache mechanism
AssigneeIntel Corporation
InventorsRyan Rakvic, Youfeng Wu, Bryan Black, John Shen
Life of this patent
Estimating the term…
Abstract
According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital loads to be processed at the CPU, and a third cache memory coupled to the CPU, the first cache memory and the second cache memory to store non-vital loads to be processed at the CPU.
Claims23
A system comprising:
- a central processing unit (CPU);
- a first cache memory, coupled to the CPU, to store only data for vital loads that are to be immediately processed at the CPU;
- a second cache memory, coupled to the CPU and the first cache, to store non-vital loads to be processed at the CPU;
- and
- a third cache memory, coupled to the CPU and the second cache memory, to store data for semi-vital loads to be processed at the CPU, wherein vital loads update the first cache memory and the second cache memory.
2 more elements
A method comprising:
- identifying load instructions having a first vitality level by filtering out load instructions having a dependence distance greater than a predetermined clock cycle;
- identifying load instructions having a second vitality level;
- assigning load instructions having the first vitality level to be stored in a first cache memory;
- and
- assigning load instructions having the second vitality level in a second cache memory;
- identifying load instructions having a third vitality level after identifying load instructions having the first vitality level;
- and
- assigning load instructions having the third vitality level to be stored in a third cache memory, wherein vital loads update the first cache memory and the second cache memory.
5 more elements
A computer system comprising:
- a central processing unit (CPU);
- a first cache memory, coupled to the CPU, to store only data for vital loads that are to be immediately processed at the CPU;
- a second cache memory, coupled to the CPU, to store data for semi-vital loads to be processed at the CPU
- a third cache memory, coupled to the CPU the first cache memory and the second cache memory, to store non-vital loads to be processed at the CPU, wherein vital loads update the first cache memory and the third cache memory;
- a chipset coupled to the CPU;
- and
- a main memory device coupled to the chipset.
4 more elements
Dependencies are inferred from the claim text.