Contention resolution in a memory management system
AssigneeLucent Technologies Inc.
InventorPeter J. Zievers
Life of this patent
Estimating the term…
Abstract
A memory management system for resolving contention for access to a plurality of memories. Signals are continuously applied to an access flow regulator indicating the busy/idle state of each memory. The access flow regulator uses the received signals to determine the present busy/idle state of each of the memories. Requests are applied to the access flow regulator for read and write access to the memories. The access flow regulator operates in response to a determination that one of the memories is currently idle for granting a request access to a memory as soon as it switches from a busy to and idle state.
Claims20
A method of operating a memory management system to resolve contention for access to a data bus extending to a plurality of memories;
- said method comprising the steps of:
- generating requests for a reading and writing of data in said memories;
- generating signals indicating a busy/idle state of each of said memories;
- extending said signals from said memories to an access flow regulator over a request bus comprising separate conductors independent of said data bus with each conductor being individual to a different one of said memories;
- operating said access flow regulator in response to a receipt of said signals to determine a busy/idle state of each of said memories;
- applying said requests to said access flow regulator;
- and
- operating said access flow regulator in response to a determination that one of said memories is currently idle for granting a request for access to said data bus for a reading or writing of data in said one memory.
A memory management system adapted to resolve contention for access to a data bus extending to a plurality of memories;
- said system comprising:
- apparatus for generating requests for access to said data bus for a reading and writing of data in said memories;
- apparatus for generating signals indicating a present busy/idle state of each of said memories;
- apparatus independent of said data bus for extending said signals from said memories to an access flow regulator over a request bus comprising separate conductors with each conductor being individual to a different one of said memories;
- apparatus for operating said access flow regulator in response to a receipt of said signals to determine a present busy/idle state of each of said memories;
- apparatus for applying said requests to said access flow regulator;
- and
- apparatus for operating said access flow regulator in response to a determination that one of said memories is currently idle for granting a request for access to said data bus for the reading or writing of data in said one memory.
Dependencies are inferred from the claim text.