Bit exactness support in dual-MAC architecture
AssigneeFreescale Semiconductor, Inc.
InventorsDror Halahmi, Yoram Salant
Life of this patent
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Abstract
An arrangement (200) and method for bit exactness support in dual-MAC architecture by detecting when underflow or overflow conditions will occur, and for operating the dual-MAC arrangement in single-MAC mode for at least one cycle upon such detection. This produces the advantages of providing dual-MAC execution with saturation capabilities, with only a small degradation in performance, while employing detection logic that is very small and simple compared to the logic required for a conventional full saturation dual-MAC architecture.
Claims19
An arrangement for bit exactness support in dual-MAC architecture, comprising:
- a dual-MAC arrangement for performing multiply-accumulate arithmetic operations on digital values A, B, C, D and E to produce a result E=<E+<C*D>+<A*B>>, where ‘+’ represents addition, ‘*’ represents multiplication, and ‘<>’ represents saturation;
- and
- a detector and enabler for detecting when an underflow or overflow condition will occur from adding C*D, and for enabling the dual-MAC arrangement to operate in single-MAC mode for at least a cycle upon such detection.
A method for bit exactness support in dual-MAC architecture, the method comprising:
- providing a dual-MAC arrangement performing multiply-accumulate arithmetic operations on digital values A, B, C, D and E to produce a result E=<E+<C*D>+<A*B>>, where ‘+’ represents represents addition, ‘*’ represents multiplication, and ‘<>’ represents saturation;
- and
- detecting when an underflow or overflow condition will occur from adding C*D, and enabling the dual-MAC arrangement to operate in single-MAC mode for at least a cycle upon such detection.
Dependencies are inferred from the claim text.