Digital systolic array architecture and method for computing the discrete Fourier transform

A digital processor architecture for computing a discrete Fourier transform, said discrete Fourier transform having a transform length N, wherein N is an integer, said processor comprising:

• at least one systolic array comprising a first plurality of processing elements;
• at least one multiplier subarray forming a portion of said at least one systolic array, said at least one multiplier array consisting of N divided by a base b linearly aligned multiplier systolic elements whereby N must be divisible by b2;
• and
• at least two complex adder subarrays, each of said at least two complex adder arrays with a first dimension consisting of N/b adder systolic elements, and a second dimension consisting of b adder systolic elements.

A digital processor architecture for computing a discrete Fourier transform, said discrete Fourier transform having a transform length N, wherein N is an integer, said processor comprising:

• at least one systolic array comprising a first plurality of processing elements;
• at least one multiplier subarray forming a portion of said at least one systolic array, said at least one multiplier array having a first dimension consisting of N/b multiplier systolic elements whereby b is a base and N must be divisible by b2;
• said at least one multiplier array having a second dimension consisting of N/b multiplier systolic elements;
• and
• at least one adder subarray forming a portion of said at least one systolic array, said at least one adder array comprising systolic elements which are at least primarily adder systolic elements, said at least one adder subarray consisting of an order of N times an order of N systolic elements.