Movable tap finite impulse response filter

An FIR filter apparatus having N taps, N being a positive integer of at least two, said FIR filter apparatus comprising:

• a coefficient generator to generate N coefficients, one for each of the N taps;
• a shared wiring responsive to an output of said coefficient generator;
• N memories, each of said memories responsive to said shared wiring to store a respective one of the N coefficients;
• and
• an FIR filter comprising N filter stages, each one of the N filter stages being responsive to one of the N coefficients stored in a corresponding one of said N memories.

An FIR filter apparatus comprising:

• coefficient generator means for generating first and second coefficients;
• controller means for synchronizing said coefficient generator;
• first control conductor means for transferring a first control signal from said controller means;
• second control conductor means for transferring a second control signal from said controller means;
• shared wiring means for transferring the first and second coefficients from said coefficient generator means;
• input means for inputting a signal;
• first memory means for storing the first coefficient transferred by said shared wiring means in response to said first control signal transferred by said first control conductor means;
• first multiplier means for multiplying the first coefficient stored in said first memory means by the signal input to said input means;
• first delay means for delaying the signal input to said input means;
• second memory means for storing the second coefficient transferred by said shared wiring means in response to said second control signal transferred by said second control conductor means;
• and
• second multiplier means for multiplying the second coefficient stored in said second memory means by the signal delayed by said first delay means.

An FIR filter apparatus having N taps, N being a positive integer of at least two, said FIR filter apparatus comprising:

• coefficient generator means for generating N coefficients, one for each of the N taps;
• shared wiring means for transferring the N coefficients from said coefficient generator means;
• N memory means, each of said memory means responsive to said shared wiring means for storing a respective one of the N coefficients;
• and
• FIR filter means for filtering an input signal comprising N filter stages, each one of the N filter stages being responsive to one of the N coefficients stored in a corresponding one of said N memory means.

A method of filtering a signal comprising:

• (a) generating first and second coefficients;
• (b) synchronizing the generation of the first and second coefficients from step (a);
• (c) transferring a first control signal from step (b);
• (d) transferring a second control signal from step (b);
• (e) providing a shared wiring for transferring the first and second coefficients;
• (f) inputting a signal;
• (g) storing the first coefficient transferred in step (e) in response to said first control signal transferred in step (c);
• (h) multiplying the first coefficient stored in step (g) by the signal input in step (f);
• (i) delaying the signal input in step (f);
• (j) storing the second coefficient transferred in step (e) in response to said second control signal transferred in step (d);
• and
• (k) multiplying the second coefficient stored in step (j) by the signal delayed in step (i).

A method of filtering a signal comprising:

• (a) generating N coefficients;
• (b) providing a shared wiring for transferring the N coefficients generated in step (a);
• (c) storing the N coefficients transferred in step (b);
• (d) filtering an input signal responsive to the N coefficients stored step (c);
• and
• (e) synchronizing step (a) and step (c).

A method of filtering a signal comprising:

• (a) generating N coefficients;
• (b) providing a shared wiring for transferring the N coefficients from step (a);
• (c) generating a selection signal;
• (d) storing the N coefficients transferred in step (b) in response to the selection generated in step (c);
• (e) filtering a signal responsive to the N coefficients stored in step (d);
• and
• (f) synchronizing step (a) with step (d).

An Ethernet transceiver, comprising:

• an input to input an input signal into an Ethernet cable;
• an output to output an output signal from the Ethernet cable, the output signal corresponding to the input signal and having an echo;
• an FIR filter comprising:
• a coefficient generator to generate first and second coefficients;
• a first control conductor;
• a second control conductor;
• a controller coupled to a first end of said first control conductor and a first end of said second control conductor;
• a shared wiring, a first end of the shared wiring being coupled to said coefficient generator;
• an input;
• a first memory coupled to a second end of said shared wiring and coupled to a second end of said first control conductor to store the first coefficient in response to said controller;
• a first multiplier responsive to the first coefficient stored in said first memory and said input;
• a first delay circuit responsive to said input;
• a second memory coupled to the second end of said shared wiring and coupled to a second end of said second control conductor to store the second coefficient in response to said controller;
• and
• a second multiplier responsive to the second coefficient stored in said second memory and said first delay circuit.

An Ethernet transceiver, comprising:

• an input to input an input signal into an Ethernet cable;
• an output to output an output signal from the Ethernet cable, the output signal corresponding to the input signal and having an echo;
• an FIR apparatus having N taps, N being a positive integer of at least 2, comprising:
• a coefficient generator to generate N coefficients, one for each of the N taps;
• a shared wiring responsive to an output of said coefficient generator;
• N memories, each of said memories responsive to said shared wiring to store a respective one of the N coefficients;
• and
• an FIR filter comprising N filter stages, each one of the N filter stages being responsive to one of the N coefficients stored in a corresponding one of said N memories.

An Ethernet transceiver, comprising:

• input means for inputting an input signal into an Ethernet cable;
• output means for outputting an output signal from the Ethernet cable, the output signal corresponding to the input signal and having an echo;
• FIR filter means comprising:
• coefficient generator means for generating first and second coefficients;
• controller means for synchronizing said coefficient generator;
• first control conductor means for transferring a first control signal from said controller means;
• second control conductor means for transferring a second control signal from said controller means;
• shared wiring means for transferring the first and second coefficients from said coefficient generator means;
• input means for inputting a signal;
• first memory means for storing the first coefficient transferred by said shared wiring means in response to said first control signal transferred by said first control conductor means;
• first multiplier means for multiplying the first coefficient stored in said first memory means by the signal input to said input means;
• first delay means for delaying the signal input to said input means;
• second memory means for storing the second coefficient transferred by said shared wiring means in response to said second control signal transferred by said second control conductor means;
• and
• second multiplier means for multiplying the second coefficient stored in said second memory means by the signal delayed by said first delay means.

An Ethernet transceiver, comprising:

• input means for inputting an input signal into an Ethernet cable;
• output means for outputting an output signal from the Ethernet cable, the output signal corresponding to the input signal and having an echo;
• FIR apparatus means having N taps, N being a positive integer of at least 2, comprising:
• coefficient generator means for generating N coefficients, one for each of the N taps;
• shared wiring means for transferring the N coefficients from said coefficient generator means;
• N memory means, each of said memory means responsive to said shared wiring means for storing a respective one of the N coefficients;
• and
• FIR filter means for filtering an input signal comprising N filter stages, each one of the N filter stages being responsive to one of the N coefficients stored in a corresponding one of said N memory means.