Operation circuit and operation control method thereof

A product-sum operation circuit comprising:

• a pulse width/digital conversion circuit which converts a pulse signal having a pulse width representing an operand value into a digital signal;
• a sorting circuit which outputs, in descending or ascending order of magnitude, a plurality of operand values converted into digital signals by said pulse width/digital conversion circuit;
• a multiplication circuit which multiplies each operand value output from said sorting circuit by a corresponding operand value;
• an accumulated sum circuit which calculates an accumulated sum of multiplication results by said multiplication circuit;
• and
• a D/A conversion circuit which converts each operand value output from said sorting circuit as a digital value into an analog signal and supplies the analog signal to said multiplication circuit,
• wherein said pulse width/digital conversion circuit comprises
• a first counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal,
• said D/A conversion circuit including a digital/pulse width conversion circuit which converts each digital operand value into a pulse signal having a pulse width corresponding to the operand value, said digital/pulse width conversion circuit comprising:
• a second counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of pulse generation circuits each of which compares the digital input value from said sorting circuit with the common count value output from said second counter and generates one of an output pulse signal having a time width from a predetermined time to a time when the input value coincides with the count value and an output pulse signal having a time width from a time when a value obtained by subtracting the input value from a predetermined maximum count value coincides with the count value to a time when the count value reaches the maximum count value.

A product-sum operation circuit comprising:

• a pulse width/digital conversion circuit which converts a pulse signal having a pulse width representing an operand value into a digital signal;
• a sorting circuit which outputs, in descending or ascending order of magnitude, a plurality of operand values converted into digital signals by said pulse width/digital conversion circuit;
• and
• a plurality of operation blocks, each including
• a multiplication circuit which multiplies each operand value output from said sorting circuit by a corresponding operand value, and
• an accumulated sum circuit which calculates an accumulated sum of multiplication results by said multiplication circuit,
• wherein said pulse width/digital conversion circuit comprises
• a counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal,
• each of the plurality of operand values includes a label, and each operand value is multiplied in the operation block corresponding to the label.

A product-sum operation circuit comprising:

• a pulse width/digital conversion circuit which converts a pulse signal having a pulse width representing an operand value into a digital signal;
• a sorting circuit which outputs, in descending or ascending order of magnitude, a plurality of operand values converted into digital signals by said pulse width/digital conversion circuit;
• a multiplication circuit which multiplies each operand value output from said sorting circuit by a corresponding operand value;
• and
• an accumulated sum circuit which calculates an accumulated sum of multiplication results by said multiplication circuit,
• wherein said pulse width/digital conversion circuit comprises
• a counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal,
• wherein said multiplication circuit executes a weighting operation of assigning a weight value to each operand value.

A product-sum operation circuit comprising:

• a pulse width/digital conversion circuit which converts a pulse signal having a pulse width representing an operand value into a digital signal;
• a sorting circuit which outputs, in descending or ascending order of magnitude, a plurality of operand values converted into digital signals by said pulse width/digital conversion circuit;
• a multiplication circuit which multiplies each operand value output from said sorting circuit by a corresponding operand value;
• and
• an accumulated sum circuit which calculates an accumulated sum of multiplication results by said multiplication circuit,
• wherein said pulse width/digital conversion circuit comprises
• a counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal,
• wherein the plurality of operand values are digital signals, and said sorting circuit outputs the plurality of operand values in descending or ascending order of magnitude by using an associative memory.

A product-sum operation circuit comprising:

• a pulse width/digital conversion circuit which converts a pulse signal having a pulse width representing an operand value into a digital signal;
• a sorting circuit which outputs, in descending or ascending order of magnitude, a plurality of operand values converted into digital signals by said pulse width/digital conversion circuit;
• a multiplication circuit which multiplies each operand value output from said sorting circuit by a corresponding operand value;
• an accumulated sum circuit which calculates an accumulated sum of multiplication results by said multiplication circuit,
• wherein said pulse width/digital conversion circuit comprises
• a counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal;
• and
• a signal output circuit which outputs a voltage signal which monotonically increases or decreases over time to said multiplication circuit in accordance with the output from said sorting circuit.

A product-sum operation circuit comprising:

• a pulse width/digital conversion circuit which converts a pulse signal having a pulse width representing an operand value into a digital signal;
• a sorting circuit which outputs, in descending or ascending order of magnitude, a plurality of operand values converted into digital signals by said pulse width/digital conversion circuit;
• a multiplication circuit which multiplies each operand value output from said sorting circuit by a corresponding operand value;
• and
• an accumulated sum circuit which calculates an accumulated sum of multiplication results by said multiplication circuit,
• wherein said pulse width/digital conversion circuit comprises
• a counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal,
• wherein said multiplication circuit receives a voltage value corresponding to the operand value as a control voltage of a voltage controlled current source and a voltage controlled resistive device and outputs a multiplication result as a voltage value.

A method of executing a product-sum operation, comprising the steps of:

• (a) converting a pulse signal having a pulse width representing an operand value into a digital signal;
• (b) outputting, in descending or ascending order of magnitude, the plurality of operand values converted into the digital signals;
• (c) multiplying each output operand value by a corresponding operand value;
• and
• (d) calculating an accumulated sum of multiplication results in the step (c), wherein the step (a) comprises the steps of
• (a-1) causing a counter to count a clock and output a count value as a digital signal,
• (a-2) causing a plurality of trailing edge latch circuits to latch a common count value output from the counter at a trailing edge of the input pulse signal
• (a-3) causing a leading edge latch circuit to latch the count value output from said counter at a leading edge of the pulse signal in correspondence with each of the plurality of trailing edge latch circuits, and
• (a-4) causing a subtraction circuit to operate and output a difference between a digital output value from said trailing edge latch circuit and a digital output value from said leading edge latch circuit in correspondence with each of the plurality of trailing edge latch circuits.

An operation circuit which calculates an accumulation value of operation results by parallel operation processing, comprising:

• a plurality of analog operation circuits each of which executes operation processing of information represented by an analog signal;
• a capacitor which accumulates, as a charge amount, a sum of the operation results by said plurality of analog operation circuits;
• a comparator which converts the charge amount accumulated in said capacitor into a pulse signal having a corresponding pulse width;
• a pulse width/digital conversion circuit which converts the pulse signal into a digital signal;
• and
• a digital operation circuit which calculates the accumulation value on the basis of the converted digital signal,
• wherein said pulse width/digital conversion circuit comprises
• a counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal,
• and wherein said pulse width/digital conversion circuit further comprises, in correspondence with each of said plurality of trailing edge latch circuits,
• a leading edge latch circuit which latches the count value output from said counter at a leading edge of the pulse signal, and
• a subtraction circuit which operates and outputs a difference between a digital output value from said trailing edge latch circuit and a digital output value from said leading edge latch circuit.

An operation circuit which calculates an accumulation value of operation results by parallel operation processing comprising:

• a plurality of analog operation circuits each of which executes operation processing of information represented by an analog signal;
• a capacitor which accumulates, as a charge amount, a sum of the operation results by said plurality of analog operation circuits;
• a comparator which converts the charge amount accumulated in said capacitor into a pulse signal having a corresponding pulse width;
• a pulse width/digital conversion circuit which converts the pulse signal into a digital signal;
• and
• a digital operation circuit which calculates the accumulation value on the basis of the converted digital signal,
• wherein said pulse width/digital conversion circuit comprises
• a counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal,
• wherein said capacitor accumulates a charge amount corresponding to a partial sum of the calculated accumulation value on the basis of the input analog signal.

An operation circuit which calculates an accumulation value of operation results by parallel operation processing comprising:

• a plurality of analog operation circuits each of which executes operation processing of information represented by an analog signal;
• a capacitor which accumulates, as a charge amount, a sum of the operation results by said plurality of analog operation circuits;
• a comparator which converts the charge amount accumulated in said capacitor into a pulse signal having a corresponding pulse width;
• a pulse width/digital conversion circuit which converts the pulse signal into a digital signal;
• and
• a digital operation circuit which calculates the accumulation value on the basis of the converted digital signal,
• wherein said pulse width/digital conversion circuit comprises
• a counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal,
• wherein said digital operation circuit executes processing every time the operation processing by said plurality of analog operation circuits is ended.

An operation circuit which calculates an accumulation value of operation results by parallel operation processing comprising:

• a plurality of analog operation circuits each of which executes operation processing of information represented by an analog signal;
• a capacitor which accumulates, as a charge amount, a sum of the operation results by said plurality of analog operation circuits;
• a comparator which converts the charge amount accumulated in said capacitor into a pulse signal having a corresponding pulse width;
• a pulse width/digital conversion circuit which converts the pulse signal into a digital signal;
• and
• a digital operation circuit which calculates the accumulation value on the basis of the converted digital signal,
• wherein said pulse width/digital conversion circuit comprises
• a counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal,
• wherein said analog operation circuit executes predetermined nonlinear conversion for the analog signal.

An operation circuit which calculates an accumulation value of operation results by parallel operation processing, comprising:

• a plurality of analog operation circuits each of which executes operation processing of information represented by an analog signal;
• a capacitor which accumulates, as a charge amount, a sum of the operation results by said plurality of analog operation circuits;
• a comparator which converts the charge amount accumulated in said capacitor into a pulse signal having a corresponding pulse width;
• a pulse width/digital conversion circuit which converts the pulse signal into a digital signal;
• a digital operation circuit which calculates the accumulation value on the basis of the converted digital signal;
• and
• a D/A conversion circuit which converts an input digital signal into the analog signal and supplies the analog signal to said plurality of analog operation circuits,
• wherein said pulse width/digital conversion circuit comprises
• a counter which counts a clock and outputs a count value as a digital signal, and
• a plurality of trailing edge latch circuits each of which latches a common count value output from said counter at a trailing edge of the input pulse signal,
• said D/A conversion circuit including a digital/pulse width conversion circuit which converts the digital signal into a pulse signal having a pulse width corresponding to the digital signal value, said digital/pulse width conversion circuit comprising:
• a second counter which counts a clock and output a count value as a digital signal, and
• a plurality of pulse generation circuits each of which compares the digital input value with the common count value output from said second counter and generates one of an output pulse signal having a time width from a predetermined time to a time when the input value coincides with the count value or an output pulse signal having a time width from a time when a value obtained by subtracting the input value from a predetermined maximum count value coincides with the count value to a time when the count value reaches the maximum count value.

An operation control method for an operation circuit which calculates an accumulation value of operation results by parallel operation processing, comprising the steps of:

• (a) causing a plurality of analog operation circuits to execute operation processing of information represented by an analog signal;
• (b) causing a capacitor to accumulate a sum of results of the operation processing as a charge amount;
• (c) converting the charge amount accumulated in the capacitor into a pulse signal having a corresponding pulse width;
• (d) converting the pulse signal into a digital signal;
• and
• (e) calculating the accumulation value on the basis of the converted digital signal,
• wherein the step (d) comprises the steps of
• (d-1) causing a counter to count a clock and output a count value as a digital signal,
• (d-2) causing a plurality of trailing edge latch circuits to latch a common count value output from the counter at a trailing edge of the input pulse signal
• (d-3) causing a leading edge latch circuit to latch the count value output from said counter at a leading edge of the pulse signal in correspondence with each of the plurality of trailing edge latch circuits, and
• (d-4) causing a subtraction circuit to operate and output a difference between a digital output value from said trailing edge latch circuit and a digital output value from said leading edge latch circuit in correspondence with each of the plurality of trailing edge latch circuits.