Method for estimating EMI in a semiconductor device

#This application claims priority under 35 U.S.C. § 119(a) on Japanese Patent Application No. 2004-31951 filed on Feb. 9, 2004, the entire contents of which are hereby incorporated by reference.

#1. Field of the Invention

#The present invention relates to a method for calculating the resistance value inside a semiconductor integrated circuit.

#FIG. 1 shows a model of an internal structure of an LSI circuit.

#FIG. 2 is a concept diagram of an internal structure of an LSI circuit that is prerequisite for a resistance value calculation method of the present invention.

#FIG. 3 shows the electrical connections of three systems of FIG. 2.

#Hereinafter, embodiments of the present invention are described with reference to the drawings. It should be noted that, in the descriptions provided below, the same elements as those described in the above section of background techniques are denoted by the same reference numerals, and the detailed descriptions thereof are herein omitted.

#The present invention may be used for a purpose other than the EMI estimation. For example, the present invention can be used for extracting the resistance from the inside of an LSI circuit.

#FIG. 1 shows a model of an internal structure of a semiconductor integrated circuit (LSI circuit). The LSI internal model 1 shown in FIG. 1 includes resistance Ri, capacitor Ci and inductor Lpackage. These elements are electrically connected between external terminal VDD and external terminal VSS. Electric current Ii flows through these elements. External terminal VDD and external terminal VSS correspond to pads on a mask layout. A cell is the minimum unit in the design of the LSI circuit. The LSI circuit is designed by connecting a plurality of cells.