Shift register
AssigneeLG. Philips LCD Co., Ltd.
InventorSu Hwan Moon
Life of this patent
Estimating the term…
Abstract
An output buffer in each stage of a shift register applies a first clock signal to an output line under control of a first node and a second driving voltage to the output line under control of second and third nodes. A first node controller controls the first node using a start pulse and an output signal of the next stage. A second node controller selectively applies a voltage at a fourth node and the second driving voltage to the second node under control of the first and second clock signals. A third node controller applies the voltage at the fourth node and the second driving voltage to the third node opposite to the second node. A fourth node controller controls the fourth node such that the fourth node has a voltage opposite to the first node using a voltage at the first node and the first driving voltage.
Claims31
A shift register having a plurality of stages for shifting an input start pulse using first and second driving voltages and first and second clock signals to apply the shifted start pulse as each output signal and a next stage start pulse, each of the plurality of stages comprising:
- an output buffer for applying the first clock signal to an output line under control of a first node and for applying the second driving voltage to the output line under control of second and third nodes;
- a first node controller for controlling the first node using the start pulse and an output signal of the next stage;
- a second node controller for selectively applying a voltage at a fourth node and the second driving voltage to the second node under control of the first and second clock signals;
- a third node controller for applying the voltage at the fourth node and the second driving voltage to the third node that is opposite to the second node under control of the first and second clock signals;
- and
- a fourth node controller for controlling the fourth node such that the fourth node has a voltage opposite to the first node using a voltage at the first node and the first driving voltage.
A method of providing a shifted input start pulse from a shift register having a current stage and a next stage, the method comprising:
- applying multiple driving voltages and clock signals as well as an input start pulse to the current stage of the shift register;
- controlling a buffer to supply one of the clock signals as an output signal of the current stage during a particular period and supplies one of the multiple driving voltages as the output signal during times other than the particular period;
- controlling multiple controllers in the current stage using the input start pulse, an output signal of the next stage, the clock signals, the driving voltages, or a voltage at one of multiple nodes internal to the current stage;
- for each controller:
- limiting a voltage supplied to a gate of at least one transistor supplying one of the driving voltages as the output signal during times other than the particular period in the buffer and limiting time that the voltage is supplied to the transistor to a voltage and time less than that causing bias stress on the transistor;
- and
- shifting the input start pulse in time and supplying the shifted input start pulse as the output signal of the current stage to an input start pulse of the next stage.
A shift register having a plurality of stages supplied with an input start pulse, clock signals and driving voltages, a current stage of the plurality of stages comprising:
- multiple controllers controlled using the input start pulse, an output signal of a next stage, the clock signals, the driving voltages, or a voltage at one of multiple nodes internal to the current stage;
- a buffer that supplies one of the clock signals as an output signal during a particular period and supplies one of the driving voltages as the output signal during times other than the particular period;
- and
- for each controller:
- limiting a voltage supplied to a gate of at least one transistor supplying one of the driving voltages as the output signal during times other than the particular period in the buffer and limiting time that the voltage is supplied to the transistor to a voltage and time less than that causing bias stress on the transistor.
A shift register having a plurality of stages for shifting an input start pulse to apply the shifted start pulse as each output signal, each of the plurality of stages comprising:
- a first transistor connected between a first clock signal and an output line, applying the first clock signal to the output line during a particular period;
- a pair of transistors connected in parallel between the output line and a low-level driving voltage, applying the low-level driving voltage during times other than the particular period;
- and
- wherein the first transistor and the pair of transistors are controlled by multiple controllers in a current stage using the input start pulse, the low-level driving voltage, a high-level driving voltage, the first clock signal, a second clock signal having a voltage opposite to the first clock signal and an output signal of a next stage, the multiple controllers limiting voltages supplied to each gate the pair of transistors and time that the voltages are supplied to each gate to a voltage and time less than that causing bias stress on each gate.
Dependencies are inferred from the claim text.