Apparatus and method for on-chip jitter measurement

A method for measuring jitter of a clock signal, comprising:

• for each of a plurality of trigger signal occurrences, performing the steps of:
• receiving the clock signal, the clock signal having a significant instant;
• propagating the significant instant of the clock signal through a chain of delay elements, wherein each element of the chain has an associated delay and the chain has a total delay equal to the sum of the associated delays;
• receiving a trigger signal and delaying the received trigger signal so as to occur at a time equal to approximately half the total delay of the chain;
• detecting the propagation of the significant instant of the clock signal through each of the delay elements in the chain and producing a pulse corresponding to each of the delay elements;
• if multiple pulses are produced coincident with the trigger signal, filtering the multiple pulses to provide one filtered pulse coincident with the trigger signal;
• and
• recording the filtered pulse that is coincident with the trigger signal;
• and
• producing a jitter measurement signal responsive to a plurality of filtered pulses after the plurality of trigger signal occurrences.

A system for responding to jitter therein, comprising:

• a reference clock configured to generate a reference clock signal having an associated frequency;
• a plurality of circuits configured to receive the reference clock signal and operative to generate an input clock signal, the plurality of circuits having a first set of characteristics;
• and
• a jitter measurement sub-system configured to receive the reference clock signal and the input clock signal and operative to generate a jitter measurement output signal responsive to a significant instant of the input clock signal, wherein the jitter measurement sub-system includes:
• a plurality of delay elements having a plurality of associated delays configured to generate a synthesized signal from the reference clock signal and the input clock signal;
• and
• at least one programmable delay element having at least one associated programmable delay configured to produce a trigger signal for generating the jitter measurement output signal from the synthesized signal;
• wherein the system is operative to adjust at least one parameter of the system in accordance with the jitter measurement output signal.

A jitter measurement circuit comprising:

• a plurality of delay elements arranged in a series-connected chain having a total delay equal to a sum of each delay of the delay elements, each having an input and an output, wherein the input of the first element in the chain receives an input clock signal, the chain propagating the input clock signal through each of its delay elements, and each delay element output producing a delayed version of the propagated input clock signal on its input;
• a first set of circuitry operative to produce at an output a pulse corresponding to each delay element in response to the propagation of a significant instant of the input clock signal through the delay element, each pulse having a width that is approximately equal to the delay of the corresponding delay element;
• and
• a second set of circuitry having one storage element corresponding to each output of the first set of circuitry, and an input that receives a trigger signal that is timed to correspond to a delay that is approximately half of the total delay of the chain, and the second set of circuitry being operative to record in each corresponding storage element any pulse that is active at the time of occurrence of the trigger signal;
• a single one detector operative to select one from the recorded pulses in the storage elements at the time of occurrence of the trigger signal;
• multiple event recorder circuitry operative to capture the selected one of the recorded pulses in the single one detector upon occurrence of each of a plurality of trigger signals, wherein a jitter measurement is made based upon the captured selected pulses;
• and
• a result calculator for producing statistical information about occurrences in the chain of the significant instance of the input clock signal.