US 7,120,214 B2Granted

Synchronous signal transfer and processing device

AssigneeRenesas Technology Corp.

InventorHidehiro Takata

Life of this patent

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Abstract

A transfer circuit includes a plurality of cascaded latch circuits. Two consecutive latch circuits in the transfer circuit complementarily enter a latching state and a transparent state in response to the applied clock signal, and data/a signal is transferred through the transfer circuit in response to the clock signal. A clock control circuit is provided for controlling an operation of each of the latch circuits. The clock control circuit detects that the latch circuit in a next stage of the corresponding latch circuit enters the latching state to permits transfer of the signal/data of the corresponding latch circuit to the subsequent stage in accordance with the corresponding clock signal. It is possible to prevent the data/signal from being transferred while the latch circuit at the next stage is in the transparent state to accurately transfer the data/signal. A clock synchronous data transfer and processing device reliably preventing racing is implemented with a simple circuit configuration.

Claims20

Dependent claims

A synchronous data transfer and processing device comprising:

at least one data transfer path including a plurality of cascaded latch circuits each entering a transparent state of passing a received signal to an output node and a latching state of holding the received signal at said output node irrespectively of a change of the signal at the signal input node in accordance with a clock control signal applied at a clock input node, two consecutive latch circuits in said plurality of latch circuits being configured such that when one is in the latching state, another is in the transparent state;
and
control circuitry for generating a control signal for controlling a state of each of said plurality of latch circuits and transmitting the generated control signal to each of said plurality of latch circuits as said clock control signal, said control circuitry including a plurality of clock control circuits, arranged corresponding to the respective latch circuits, for applying the control signal to the clock input node of a corresponding latch circuit in accordance with a clock signal transmitted to the corresponding latch circuit and the clock control signal at the clock input node of the latch circuit at a next stage of the corresponding latch circuit.

A synchronous data transfer and processing device comprising:

at least one signal transfer path including a plurality of flip-flops, arranged in cascade, each including a first latch circuit and a second latch circuit complementarily entering a latching state and a transparent state;
a logical circuit, interposed at a selected position on the signal transfer path, for performing a predetermined processing on an applied signal;
and
transfer control circuitry for controlling a signal transfer operation of each of said plurality of flip-flops,
said transfer control circuitry including;
a plurality of flip-flop control circuits, arranged corresponding to said plurality of flip-flops, each for generating a control signal to a corresponding flip-flop in accordance with a clock signal transmitted to the corresponding flip-flop and the control signal for the flip-flop in a next stage of the corresponding flip-flop, each flip-flop control circuit generating the control signal to the corresponding flip-flop in accordance with the transmitted clock signal when the control signal to said flip-flop at said next stage instructs that said flip-flop at the next stage enters the latching state, and
a logical stage control circuit, arranged corresponding to the flip-flop arranged in a preceding stage of said logical circuit, for generating the control signal to said flip-flop in the preceding stage of said logical circuit in accordance with a corresponding clock signal with simulation that the flip-flop arranged at a next stage of said logical circuit is in the latching state.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/214,598Filed 9 Aug 2002
Priority: JP 2001-24377710 Aug 2001
Published: US 2003/0030472 A113 Feb 2003
Granted: 10 Oct 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G11C 19/00
Digital stores in which the information is moved stepwise
G11C 19/28
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements
H03K 5/135
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: by the use of time reference…