Pseudo SRAM having combined synchronous and asynchronous mode register set
AssigneeHynix Semiconductor Inc.
InventorSang Kwon Lee
Life of this patent
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Abstract
A PSRAM features a mode register set (MRS) for setting a mode register at a combined synchronous and asynchronous mode. The PSRAM having a combined synchronous and asynchronous mode register set includes a MRS, a mode register control unit, a plurality of control signal buffers, an address buffer, a clock buffer, and a synchronous and asynchronous detecting unit. Here, the plurality of control signal buffers, the address buffer and the clock buffers are controlled by a chip selecting signal at an asynchronous mode, and are operated synchronously with respect to an internal clock outputted from the clock buffer regardless of the chip selecting signal at a synchronous mode.
Claims18
A PSRAM having a combined synchronous and asynchronous register set, comprising:
- a MRS for setting an operating mode;
- a mode register control unit for controlling the operation of the MRS;
- a plurality of control signal buffers for buffering external control signals;
- an address buffer for buffering an address signal;
- a clock buffer for buffering a clock signal;
- and
- a synchronous and asynchronous detecting unit for detecting an internal clock outputted from the clock buffer to generate an asynchronous control signal for controlling the mode register control unit at a synchronous, asynchronous and combined mode,
- wherein the plurality of control signal buffers, the address buffer and the clock buffers are controlled by a chip selecting signal at an asynchronous mode, and are operated synchronously with respect to an internal clock outputted from the clock buffer regardless of the chip selecting signal at a synchronous mode.
Dependencies are inferred from the claim text.