System for reducing row periphery power consumption in memory devices
AssigneeTexas Instruments Incorporated
InventorsXiaowei Deng, Theodore W. Houston, Bryan D. Sheffield
Life of this patent
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Abstract
The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.
Claims4
A wordline circuitry segment in an SRAM device, the circuitry segment comprising:
- a first node coupled to a wordline enable signal;
- a second node coupled to a wordline signal;
- a third node coupled to a sleep mode assertion signal;
- a fourth node coupled to a first reference voltage;
- a fifth node coupled to a second reference voltage;
- a first transistor structure, having a first terminal coupled to the first node, a second terminal coupled to the fourth node, and a third and fourth terminal;
- a second transistor structure, having a first terminal coupled to the fourth terminal of the first transistor structure, a second terminal coupled to the fourth node, a third terminal coupled to the third terminal of the first transistor structure, and a fourth terminal coupled to the second node;
- a third transistor structure, having a first terminal coupled to the third node, a second terminal coupled to the third terminal of the first transistor structure, and a third terminal coupled to a third reference voltage;
- and
- a fourth transistor structure, having a first terminal coupled to the fifth node, a second terminal coupled to the fourth node, and a third terminal coupled to the second node.
A wordline circuitry segment in an SRAM device, the circuitry segment comprising:
- a first node coupled to a wordline enable signal;
- a second node coupled to a wordline signal;
- a third node coupled to a sleep mode assertion signal;
- a fourth node coupled to a first reference voltage;
- a fifth node coupled to a second reference voltage;
- a sixth node coupled to a third reference voltage;
- a first transistor structure, having a first terminal coupled to the first node, a second terminal, a third terminal coupled to the fifth node, and a fourth terminal;
- a second transistor structure, having a first terminal coupled to the fourth terminal of the first transistor structure, a second terminal coupled to the fourth node, a third terminal coupled to the fifth node, and a fourth terminal coupled to the second node;
- a third transistor structure, having a first terminal coupled to the third node, a second terminal coupled to a fourth reference voltage, and a third terminal coupled to the second terminal of the first transistor structure;
- and
- a fourth transistor structure, having a first terminal coupled to the sixth node, a second terminal coupled to the first terminal of the second transistor structure, and a third terminal coupled to the fifth node.
Dependencies are inferred from the claim text.