US 7,120,080 B2 · Dual port semiconductor memory device

Abstract

A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.

Claims21

Dependent claims

A dual port semiconductor memory cell, comprising:

a first CMOS inverter including a first NMOS transistor, a first PMOS transistor, an input port, and an output port;
a second CMOS inverter including a second NMOS transistor, a second PMOS transistor, an input port coupled to the output port of the first CMOS inverter and constitutes a first memory node together with the output port of the first CMOS inverter, and an output port coupled to the input port of the first CMOS inverter and constitutes a second memory node together with the input port of the first CMOS inverter;
a third NMOS transistor having a gate coupled to a wordline, a drain coupled to a bitline, and a source coupled to the first memory node;
a fourth NMOS transistor having a gate coupled to the wordline, a drain coupled to a complementary bitline, and a source coupled to the second memory node;
and
a third PMOS transistor having a gate coupled to a scan address line, a source coupled to the second memory node, and a drain coupled to a scan data-out line;
where the memory cell is divided into first and second n-wells where P+ active regions are formed and first and second p-wells where N+ active regions are formed.

4 more elements

A dual port semiconductor memory device with a substrate including a plurality of memory cells, each memory cell comprising:

a first CMOS inverter including a first NMOS transistor, a first PMOS transistor, an input port, and an output port;
a second CMOS inverter including a second NMOS transistor, a second PMOS transistor, an input port coupled to the output port of the first CMOS inverter and constitutes a first memory node together with the output port of the first CMOS inverter, and an output port coupled to the input port of the first CMOS inverter and constitutes a second memory node together with the input port of the first CMOS inverter;
a third NMOS transistor having a gate coupled to a wordline, a drain coupled to a bitline, and a source coupled to the first memory node;
a fourth NMOS transistor having a gate coupled to the wordline, a drain coupled to a complementary bitline, and a source coupled to the second memory node;
and
a third PMOS transistor having a gate coupled to a scan address line, a source coupled to the second memory node, and a drain coupled to a scan data-out line;
where the plurality of memory cells are arranged in symmetry with respect to boundaries thereamong;
and
where the memory cell is divided into first and second n-wells where P+ active regions are formed and first and second p-wells where N+ active regions are formed.

6 more elements

A dual port semiconductor memory device comprising:

a semiconductor substrate which is divided into first and second n-wells having P+ active regions and first and second p-wells having N+ active regions, the second p-well being located between the first and second n-wells and the first and second p-wells including a plurality of memory cells located at either side of the first n-well;
a wordline and a scan address line;
a pair of bitlines, comprised of a bitline and a complementary bitline, and a scan data-out line;
where each of the plurality of memory cells comprises:
a first CMOS inverter which includes a first NMOS transistor, a first PMOS transistor, an input port, and an output port;
a second CMOS inverter which includes a second NMOS transistor, a second PMOS transistor, an input port, coupled to the output port of the first CMOS inverter and constitutes a first memory node together with the output port of the first CMOS inverter, and an output port, coupled to the input port of the first CMOS inverter and constitutes a second memory node together with the input port of the first CMOS inverter;
a third NMOS transistor having a gate coupled to the wordline, a drain coupled to the bitline, and a source coupled to the first memory node;
a fourth NMOS transistor having a gate coupled to the wordline, a drain coupled to the complementary bitline, and a source coupled to the second memory node;
and
a third PMOS transistor having a gate coupled to the scan address line, a source coupled to the second memory node, and a drain coupled to the scan data-out line,
where the first and third NMOS transistors are formed in the N+ active regions of the first p-well, the second and fourth NMOS transistors are formed in the N+ active regions of the second p-well, the first and second PMOS transistors are formed in the P+ regions of the first n-well, and the third PMOS transistor is formed in the P+ active region of the second n-well.

8 more elements

Dependencies are inferred from the claim text.

Dual port semiconductor memory device

Life of this patent

Dual port semiconductor memory device

Life of this patent

Abstract

Claims21