Flash/dynamic random access memory field programmable gate array
AssigneeActel Corporation
InventorsJohn McCollum, Vidya Bellippady, Gregory Bakker
Life of this patent
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Abstract
A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
Claims4
A method for providing a circuit for selectively interconnecting two nodes in an integrated circuit device, said method comprising:
- providing a memory array having a plurality of wordlines and a plurality of bitlines;
- providing a refresh transistor having a source coupled to one of said plurality of bitlines, a control gate coupled to a dynamic random access memory wordline, and a drain;
- providing a switching transistor having a gate coupled to said drain of said refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes;
- and
- providing an address decoder for supplying periodic signals to drive said wordlines and said dynamic random access memory wordline.
Dependencies are inferred from the claim text.