Synchronous semiconductor memory

A semiconductor memory comprising:

• a row address register which registers a row address signal;
• a row address driver which drives a row address of a memory cell array by using the row address signal;
• a command detecting circuit which detects an operation mode of each of successive first and second cycles, wherein when the operation mode of the first cycle is a write mode, the write mode is completed by the first cycle registering the row address signal to the row address register and the second cycle driving the row address of the memory cell array;
• and
• a controller which controls the row address register and the row address driver, wherein when the operation modes of the first and second cycles are a refresh mode, in the second cycle, the row address driver drives the row address by using a refresh counter address without a driving of the row address based on the row address signal.

A semiconductor memory comprising:

• a row address register which registers a row address signal;
• a row address driver which drives a row address of a memory cell array by using the row address signal;
• a command detecting circuit which detects an operation mode of each of successive first and second cycles, wherein when the operation mode of the first cycle is a write mode, the write mode is completed by the first cycle registering the row address signal to the row address register and the second cycle driving the row address of the memory cell array;
• and
• a controller which controls the row address register and the row address driver, wherein when the operation mode of the first cycle is a refresh mode and the operation mode of the second cycle is the write mode, in the second cycle, the row address driver is to be non-operated and the row address register registers the row address signal.

A semiconductor memory comprising:

• a command detecting circuit which detects first, second and third commands, wherein when the first and second commands are detected, a write mode is executed, and when the first and third commands are detected, a auto-refresh mode is executed;
• a write & auto-refresh controller which outputs a first control signal when the first and third commands are detected;
• an auto-refresh circuit which outputs a second control signal in the auto-refresh mode;
• a row address register which registers a row address signal, wherein the row address register is to be operated when the first command is detected;
• and
• a row address driver which drives a row address of a memory cell array by using the row address signal, wherein the row address driver is to be non-operated except a case when the first control signal is inputted into the row address driver;
• wherein the case is that the second control signal is inputted into the row address driver and the first command is detected.