Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching

An integrated circuit chip, comprising:

• a plurality of first-in first-out (FIFO) memory devices that are collectively configured to support a multi-queue operating mode that supports write queue pointer changes that are free of corresponding write operations, wherein each of said plurality of FIFO memory devices comprises a respective double-buffered read data path.

An integrated circuit chip, comprising:

• a plurality of first-in first-out (FIFO) memory devices that are collectively configured to support a multi-queue operating mode that supports write queue pointer changes that are free of corresponding write operations and further supports write path queue switching on every write cycle in both SDR and DDR write modes and read path queue switching on every read cycle in both SDR and DDR read modes.

An integrated circuit chip, comprising:

• a plurality of first-in first-out (FIFO) memory devices that are collectively configured to support a multiplexer operating mode that provides read path queue switching, which is free of read word fall-through, on every read cycle in both SDR and DDR read modes.

An integrated circuit chip, comprising:

• a plurality of first-in first-out (FIFO) memory devices that are collectively configured to support a demultiplexer operating mode that provides write path queue switching, which is free of write word fall-through, on every write cycle in both SDR and DDR write modes.

An integrated circuit chip, comprising:

• a plurality of first-in first-out (FIFO) memory devices that are individually configured to have at least double-buffered read data paths and collectively configured to support a multi-queue operating mode that provides write path queue switching on every write cycle and read path queue switching on every read cycle.