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US 7,120,072 B2Granted
Two transistor gain cell, method, and system
AssigneeIntel Corporation
InventorsYibin Ye, Dinesh Somasekhar, Muhammad M Khellah, Fabrice Paillet, Stephen H Tang, Ali Keshavarzi, Shih-Lien L Lu, Vivek K De
Life of this patent
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Abstract
A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.
Claims25
A method of reading a two transistor memory cell comprising:
- precharging a read bit line to increase a voltage differential between a storage node in the two transistor memory cell and the read bit line;
- modifying a voltage on a read word line coupled to the two transistor memory cell;
- and sensing a voltage on the read bit line;
- wherein precharging comprises reducing a read bit line voltage coupled to a source/drain node of a P-type isolated gate transistor within the two transistor memory cell, and wherein the storage node corresponds to a gate node of the P-type isolated gate transistor.
1 more element
A method of reading a two transistor memory cell comprising:
- precharging a read bit line to increase a voltage differential between a storage node in the two transistor memory cell and the read bit line;
- modifying a voltage on a read word line coupled to the two transistor memory cell;
- and sensing a voltage on the read bit line;
- wherein precharging comprises increasing a read bit line voltage coupled to a source/drain node of an N-type isolated gate transistor within the two transistor memory cell, and wherein the storage node corresponds to a gate node of the N-type isolated gate transistor.
1 more element
A memory device comprising:
- a plurality of two transistor gain cells arranged in a column;
- a write bit line and a read bit line coupled to the plurality of two transistor gain cells;
- and
- a driver circuit coupled to precharge the read bit line when performing a read, wherein the driver circuit includes circuitry to reduce a voltage on the read bit line.
1 more element
A memory device comprising:
- a plurality of two transistor gain cells arranged in a colunm;
- a write bit line and a read bit line coupled to the plurality of two transistor gain cells;
- and a driver circuit coupled to precharge the read bit line when performing a read, wherein the driver circuit includes circuitry to increase a voltage on the read bit line.
A memory device comprising:
- a write bit line and a read bit line;
- a P-type write transistor having a source/drain node coupled to the write bit line and a source/drain node coupled to a storage node;
- a P-type read transistor having a gate node coupled to the storage node and a source/drain node coupled to the read bit line;
- and
- a write bit line driver coupled to the write bit line to provide a voltage on the storage node that creates a positive voltage between the storage node and the read bit line when writing either a “0” or a “1”.
2 more elements
A memory device comprising:
- a write bit line and a read bit line;
- an N-type write transistor having a source/drain node coupled to the write bit line and a source/drain node coupled to a storage node;
- a N-type read transistor having a gate node coupled to the storage node and a source/drain node coupled to the read bit line;
- and
- a write bit line driver coupled to the write bit line to provide a voltage on the storage node that creates a negative voltage between the storage node and the read bit line when writing either a “0” or a “1”.
2 more elements
An electronic system comprising:
- an antenna;
- a first integrated circuit coupled to the antenna;
- and
- a second integrated circuit including a memory device, the memory device comprising a plurality of two transistor gain cells arranged in a column, a write bit line and a read bit line coupled to the plurality of two transistor cells, and a driver circuit coupled to precharge the read bit line when performing a read, wherein the driver circuit includes circuitry to reduce a voltage on the read bit line.
1 more element
Dependencies are inferred from the claim text.