US 7,120,070 B2 · Method for testing the serviceability of bit lines in a DRAM memory device

Abstract

DRAM memory device (1) comprising at least one array of memory cells (2, 3, 4, 5), each memory cell (12) being connected to a bit line (BL) and a word line (WL), each of said bit lines (BL) being connected to a sense amplifier and a pre-charge circuit (15); a controllable active-current generator (7, 8, 9, 10) for providing power to the sense amplifiers and pre-charge circuits (15) for a time interval that is limited by a time at which a command for a read or write access is applied to the DRAM memory device (1) and an assigned switching time; a controllable standby-current generator (6) for providing power to the sense amplifiers and pre-charge circuits (15) after the switching time; a control circuit (11) for receiving external data, address and control signals (C, A, D) and for controlling the active-current generator (7, 8, 9, 10) and the standby-current generator (6); wherein the control circuit (11) is adapted to control the time for switching the respective power generator (6, 7, 8, 9, 10) to the sense amplifiers and to the pre-charge circuits (15) subject to an external test mode signal for reducing the overall testing time in a test of the serviceability of the bit lines (BL), sense amplifiers and pre-charge circuits (15).

Claims12

Dependent claims

A method for testing the serviceability of bit lines, sense amplifiers and pre-charge circuits in a DRAM memory device comprising the following steps:

(a) setting a DRAM memory device in a test mode;
(b) applying a write command to the DRAM memory device for writing a predetermined test data to a memory cell connected to a bit line and contemporaneously switching on an active-current generator for providing power to a sense amplifier and pre-charge circuit associated to the bit line;
(c) switching off the active-current generator and switching a standby-current generator to the sense amplifier and the pre-charge circuit of the bit line at a controllable switching time, wherein the switching time is earlier with respect to a switching time in a normal operation mode;
(d) performing a pre-charge operation on the bit line by closing a word line associated to the memory cell and applying a pre-charge voltage to the bit line by the associated pre-charge circuit;
(e) reading the data stored in the memory cell;
and
(f) comparing the read data with the predetermined test data.

4 more elements

A DRAM memory device comprising:

(a) at least one array of memory cells, each memory cell being connected to a bit line and a word line, each of said bit lines being connected to a sense amplifier and a pre-charge circuit;
(b) a controllable active-current generator for providing power to the sense amplifiers and pre-charge circuits for a time interval that is limited by a time at which a command for a read or write access is applied to the DRAM memory device and an assigned switching time;
(c) a controllable standby-current generator for providing power to the sense amplifiers and pre-charge circuits after the switching time;
(d) a control circuit for receiving external data, address and control signals and for controlling the active-current generator and the standby-current generator;
wherein the control circuit is adapted to control the time for switching the respective power generator to the sense amplifiers and to the pre-charge circuits subject to an external test mode signal for reducing the overall testing time in a test of the serviceability of the bit lines, sense amplifiers and pre-charge circuits.

2 more elements

Dependencies are inferred from the claim text.

Method for testing the serviceability of bit lines in a DRAM memory device

Life of this patent

Method for testing the serviceability of bit lines in a DRAM memory device

Life of this patent

Abstract

Claims12