Memory with data latching circuit including a selector

A circuit for writing data to a memory comprising:

• a selector configured to receive a delayed data signal, a data strobe signal, and an inverted data strobe signal, the selector configured to:
• provide a first strobe signal for latching a logic high data signal in response to a rising edge of the data strobe signal and a logic low delayed data signal;
• provide the first strobe signal for latching a logic low data signal in response to a falling edge of the inverted data strobe signal and a logic high delayed data signal;
• provide a second strobe signal for latching a logic high data signal in response to a rising edge of the inverted data strobe signal and a logic low delayed data signal;
• and
• provide the second strobe signal for latching a logic low data signal in response to a falling edge of the data strobe signal and a logic high delayed data signal.

A memory comprising:

• a data in/out circuit comprising:
• a first receiver configured to provide a data strobe signal in response to an external data strobe signal;
• a second receiver configured to provide an inverted data strobe signal in response to an external inverted data strobe signal;
• a third receiver configured to provide a data signal in response to an external data signal;
• a delay configured to delay the data signal to provide a delayed data signal;
• a selector configured to provide a first strobe signal and a second strobe signal in response to the data strobe signal, the inverted data strobe signal, and the delayed data signal;
• a first latch configured to latch the data signal in response to the first strobe signal to provide a rising edge data signal;
• and
• a second latch configured to latch the data signal in response to the second strobe signal to provide a falling edge data signal.

A circuit for latching data into a memory comprising:

• means for latching a logic high data signal into the memory in response to a rising edge of a data strobe signal and a logic low delayed data signal;
• means for latching a logic low data signal into the memory in response to a falling edge of an inverted data strobe signal and a logic high delayed data signal;
• means for latching a logic high data signal into the memory in response to a rising edge of the inverted data strobe signal and a logic low delayed data signal;
• and
• means for latching a logic low data signal into the memory in response to a falling edge of the data strobe signal and a logic high delayed data signal.

A method of latching data into a memory, the method comprising:

• latching a logic high rising edge data signal into the memory in response to a rising edge of a data strobe signal;
• latching a logic low rising edge data signal into the memory in response to a falling edge of an inverted data strobe signal;
• latching a logic high falling edge data signal into the memory in response to a rising edge of the inverted data strobe signal;
• and
• latching a logic low falling edge data signal into the memory in response to a falling edge of the data strobe signal.

A method for receiving data into a memory, the method comprising:

• receiving a data signal, a data strobe signal, and an inverted data strobe signal;
• delaying the data signal to provide a delayed data signal;
• providing a first strobe signal for latching a logic high data signal in response to a rising edge of the data strobe signal and a logic low delayed data signal;
• providing the first strobe signal for latching a logic low data signal in response to a falling edge of the inverted data strobe signal and a logic high delayed data signal;
• providing a second strobe signal for latching a logic high data signal in response to a rising edge of the inverted data strobe signal and a logic low delayed data signal;
• and
• providing the second strobe signal for latching a logic low data signal in response to a falling edge of the data strobe signal and a logic high delayed data signal.

A method for writing to a memory, the method comprising:

• receiving an external data strobe signal;
• receiving an external inverted data strobe signal;
• receiving an external data signal;
• comparing the external data strobe signal to a reference voltage to provide a data strobe signal;
• comparing the external inverted data strobe signal to the reference voltage to provide an inverted data strobe signal;
• comparing the external data signal to the reference voltage to provide a data signal;
• generating a first strobe signal and a second strobe signal in response to the data strobe signal, the inverted data strobe signal, and the data signal;
• latching the data signal in response to the first strobe signal to provide a rising edge data signal;
• and
• latching the data signal in response to the second strobe signal to provide a falling edge data signal.