Memory device for multiplexing input and output operation
AssigneeHynix Semiconductor Inc.
InventorSung Soo Xi
Life of this patent
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Abstract
A memory device for multiplexing an input/output operation prevents mis-operations by comparing the input addresses with the output data and improves operating speed by activating data corresponding to the input addresses by input address toggle. The memory device for multiplexing an input/output operation comprises an data output buffer, an address buffer, a comparison unit and a row activation control unit. The comparison unit compares an address outputted from the address buffer to the address bus with data inputted through the output data bus to the data output buffer, and outputs the comparison result. The row activation control unit generates a row active signal for activating a row path in response to the comparison result.
Claims7
A memory device for multiplexing an input/output operation, comprising:
- a plurality of data output buffers each buffering data of an output data bus at a read mode and outputting the buffered data to an external data bus;
- a plurality of address buffers each buffering an address of the external data bus and outputting the buffered address to an address bus;
- a plurality of comparison units each comparing an address outputted from one of the plurality of address buffers to the address bus with data inputted through the output data bus to the respective one of the plurality of data output buffers, and outputting a plurality of comparison results, respectively;
- and
- a row activation control unit for generating a row active signal which selectively activates a row path in response to the plurality of comparison results.
Dependencies are inferred from the claim text.