Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

A three-transistor EEPROM cell memory comprising:

• two global select gates running vertically;
• a plurality of bytes of eight bitlines running vertically;
• a wordline divided into a plurality of byte-wordlines running horizontally over a floating gate;
• and
• a plurality of BN+ source/drains running horizontally.

A three-transistor EEPROM cell memory comprising:

• two global select gates running horizontally;
• a plurality of bytes of eight bitlines running vertically;
• a wordline divided into a plurality of byte-wordlines running vertically over a floating gate;
• and
• a plurality of BN+ source/drains running vertically.

A nonvolatile memory comprising:

• an array of three-transistor EEPROM cells, each cell comprising:
• two global select gates;
• a plurality of bytes of eight bitlines;
• a wordline divided into a plurality of byte-wordlines running over a floating gate;
• a plurality of cells with BN+ source/drains;
• and
• a plurality of byte-wordline decoders formed in an undivided triple well and located outside of said array of three-transistor EEPROM cells and connected to said byte-wordlines by a plurality of metal lines.