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US 7,120,060 B2Granted
Memory device with non-volatile reference memory cell trimming capabilities
AssigneeMicron Technology, Inc.
InventorTheodore T. Pekny
Life of this patent
Estimating the term…
Abstract
A non-volatile memory device comprising a primary memory array, at least one non-volatile reference memory cell and sense circuitry. The primary memory array has a plurality of memory cells. The sense circuitry is used to monitor the logic state of the memory cells. In addition, the memory device has an input connection to couple an external reference current to the sense circuitry to be used during the programming of the reference memory cell.
Claims19
A method for trimming a flash reference cell located in a memory array of a memory device, the method comprising:
- erasing the flash reference cell below a desired Vt level;
- applying a first program pulse having a predetermined voltage level and is applied for a predetermined period of time to the flash reference cell to increase a floating gate charge of the flash reference cell;
- accessing the flash reference cell to create a cell current in a bitline coupled to a drain of the reference cell;
- comparing, with a sense amplifier, the cell current with an externally provided constant reference current, wherein the constant reference current is indicative of a desired memory cell current;
- and
- applying further program pulses to the flash reference cell, while maintaining the constant reference current, when the cell current is less than the reference current until a digital output of the sense amplifier changes state to indicate that the flash reference cell is programmed to a desired level, each further program pulse having the predetermined voltage level and is applied for the predetermined period of time without change in the predetermined voltage level or predetermined period of time from the first program pulse such that all program pulses experienced by the flash reference cell are at the predetermined voltage level and for the predetermined period of time.
3 more elements
A method for trimming a reference memory cell that comprises a control gate, a drain, and a source and is located in a memory array of a memory device, the method comprising:
- erasing a floating gate of the reference memory cell to a level such that the reference memory cell is turned off when a predetermined voltage is applied to a control gate of the reference memory cell;
- applying a constant external reference current to a sense amplifier, wherein the sense amplifier is internal to the memory device;
- providing a first program pulse having a predetermined voltage level and applied for a predetermined period of time to the reference memory cell to increase a charge on the floating gate of the reference memory cell;
- coupling the predetermined voltage to the control gate;
- comparing a digitline current provided by the reference memory cell with the constant reference current using the sense amplifier;
- and
- providing additional program pulses to the reference memory cell while maintaining the constant external reference current on the sense amplifier until the digitline current is less than the reference current wherein each additional program pulse has the predetermined voltage level and is applied for the predetermined period of time without change in the predetermined voltage level or predetermined period of time from the first program pulse such that all program pulses experienced by the flash reference cell are at the predetermined voltage level and for the predetermined period of time.
4 more elements
A method for trimming non-volatile reference bits located in a memory array of a memory device, the method comprising:
- erasing each non-volatile reference bit below a desired voltage threshold;
- applying a first low level program pulse having a predetermined voltage level and applied for a predetermined period of time to each non-volatile reference bit;
- coupling a predetermined access voltage to control gates of each non-volatile reference bit to create a bit current in associated bitlines coupled to each non-volatile reference bit;
- applying a constant reference current to the memory device from a source that is external to the memory device;
- comparing the constant external reference current to the bit currents in each of the bitlines with sense amplifiers of the memory device;
- and
- applying additional program pulses to reference bits coupled to bitlines having bit current levels less than the reference current while maintaining the constant external reference current to the sense amplifiers wherein each additional program pulse has the predetermined voltage level and is applied for the predetermined period of time without change in the predetermined voltage level or predetermined period of time from the first program pulse such that all program pulses experienced by the flash reference cell are at the predetermined voltage level and for the predetermined period of time.
4 more elements
Dependencies are inferred from the claim text.