Memory array including multiple-gate charge trapping non-volatile cells

An integrated circuit memory device, comprising:

• an array of multiple-gate memory cells, the array including a plurality of sectors, a plurality of columns and a plurality of rows of multiple-gate memory cells, where each sector in the plurality of sectors includes multiple-gate memory cells in at least one row in the plurality of rows;
• multiple-gate memory cells in the array respectively comprising a semiconductor body, a plurality of gates arranged in series on the semiconductor body, the plurality of gates including a first gate in the series and a last gate in the series, a charge storage structure including charge trapping locations beneath more than one of the plurality of gates in the series, and a continuous, multiple-gate channel region in the semiconductor body beneath the plurality of gates in the series;
• a plurality of word lines, the plurality of word lines including a plurality of sets of word lines, wherein each set of word lines in the plurality of sets is coupled to multiple-gate memory cells in a corresponding row in the plurality of rows;
• a plurality of sector select lines arranged along the plurality of word lines, the plurality of sector select lines including at least one sector select line corresponding to each sector in the plurality of sectors;
• a plurality of bit lines, arranged orthogonally to the plurality of word lines, bit lines in the plurality of bit lines arranged for connection to multiple-gate memory cells in one or more columns of the plurality of columns;
• and wherein
• sectors in the plurality of sectors respectively comprise a plurality of select gates, the select gates in the plurality of select gates arranged to connect respective multiple-gate memory cells in the at least one row to a corresponding bit line in the plurality of bit lines in response to a select gate control signal, and wherein a sector select line in the plurality of sector select lines is coupled to the plurality of select gates in the at least one row within the corresponding sector to provide the select gate control signal;
• and
• a controller which controls the plurality of bit lines, the plurality of word lines and the plurality of sector select lines to conduct source and drain bias voltages to the multiple-gate memory cells in the array, and to conduct gate bias voltages to the plurality of gates in the multiple-gate memory cells in the at least one row, and to provide the select gate control signals.