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US 7,120,055 B2Granted
Flash memory device with improved programming performance
AssigneeMicron Technology, Inc.
InventorJeffrey Alan Kessenich
Life of this patent
Estimating the term…
Abstract
A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative potential to reduce the cell leakage at programming bitline potential. A programming pulse is applied to the bitline coupled to the cell to be programmed. During verification, the unselected wordlines are biased back to ground potential.
Claims20
A flash memory device comprising:
- a memory array having a plurality of flash memory cells organized in rows and columns, each column comprising a bitline coupling drain connections of the plurality of flash memory cells and each row comprising a wordline coupling control gates of the plurality of flash memory cells;
- and
- control circuitry adapted to perform a programming operation on the memory array, the programming operation comprising:
- pulsing the bitline, coupled to a flash memory cell to be programmed, with a programming pulse having a first predetermined voltage;
- biasing a selected wordline, coupled to the flash memory cell to be programmed, to a second predetermined voltage;
- and
- biasing unselected wordlines to a predetermined negative voltage.
4 more elements
A non-volatile memory device comprising:
- a memory array having a plurality of non-volatile memory cells organized in rows and columns, each column comprising a bitline and each row comprising a wordline;
- and
- control circuitry adapted to perform a programming operation on the memory array, the programming operation comprising:
- pulsing the bitline, coupled to a non-volatile memory cell to be programmed, with a programming pulse having a first positive voltage;
- biasing a selected wordline, coupled to the non-volatile memory cell to be programmed, to a second positive voltage;
- and
- biasing unselected wordlines to a predetermined negative voltage.
4 more elements
An electronic system comprising:
- a processor that generates memory control signals;
- and
- a flash memory device coupled to the processor and operating in response to the control signals, the flash memory device comprising:
- a memory array having a plurality of flash memory cells organized in rows and columns, each column comprising a bitline and each row comprising a wordline;
- and
- control circuitry adapted to perform a programming operation on the memory array, the programming operation comprising:
- pulsing the bitline, coupled to a flash memory cell to be programmed, with a programming pulse having a first predetermined voltage;
- biasing a selected wordline, coupled to the flash memory cell to be programmed, to a second predetermined voltage;
- and
- biasing unselected wordlines to a predetermined negative voltage.
7 more elements
Dependencies are inferred from the claim text.