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US 7,120,054 B2Granted
Preconditioning global bitlines
AssigneeMicron Technology, Inc.
InventorsEbrahim Abedifard, Frankie Fariborz Roohparvar
Life of this patent
Estimating the term…
Abstract
A method and apparatus for discharging global bitlines in a flash memory to a voltage sufficiently low to avoid drain disturb for non-selected cells in a programming operation. A discharge device allows discharge of global bitlines coupled to local bitlines before a programming operation.
Claims18
A system, comprising:
- a processor;
- and
- a flash memory device coupled to the processor, the flash memory device comprising:
- a plurality of floating gate memory cells arranged in a pattern of rows and columns;
- a plurality of word lines, each word line connected to multiple cells in a row of cells;
- a plurality of local bitlines, each bitline connected to multiple cells in a column of cells;
- a plurality of global bitlines, each global bitline connectable to a local bitline through a pass transistor;
- and
- a discharge circuit to discharge each global bitline to a predetermined potential.
6 more elements
A system, comprising:
- a processor;
- and
- a flash memory device coupled to the processor, the flash memory device comprising:
- an array of floating gate memory cells;
- control circuitry to read, write and erase the floating gate memory cells;
- and
- a preconditioning circuit to precondition global bitlines prior to a programming operation.
4 more elements
A processing system, comprising:
- a processor;
- and
- a flash memory device coupled to the processor, the flash memory device comprising an array of flash memory cells each comprising:
- a floating gate storage transistor, the transistor having a gate, a drain, and a source;
- and
- a preconditioning circuit to precondition global bitlines prior to a programming operation.
3 more elements
A processing system, comprising:
- a processor;
- and
- a flash memory device coupled to the processor, the flash memory device comprising an array of flash memory cells each comprising:
- a floating gate storage transistor, the transistor having a gate, a drain, and a source;
- and
- a discharge device connected between the drain and a predetermined potential, wherein the discharge device is a switch connected to its respective global bitline, to discharge its global bitline to a threshold voltage of the switch.
3 more elements
A memory device comprising:
- an array of memory cells;
- control circuitry to read, write and erase the memory cells;
- address circuitry to latch address signals provided on address input connections;
- input/output circuitry coupled to read and latch a row of data from the memory array;
- and
- a preconditioning circuit to precondition global bitlines prior to a programming operation.
3 more elements
A processing system, comprising:
- a processor;
- and
- a memory coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising:
- an array of memory cells;
- control circuitry to read, write and erase the memory cells;
- address circuitry to latch address signals provided on address input connections;
- input/output circuitry coupled to read and latch a row of data from the memory array;
- and
- a preconditioning circuit to precondition global bitlines prior to a programming operation.
6 more elements
A memory, comprising:
- an array of flash memory cells, each cell comprising:
- a floating gate storage transistor, the transistor having a gate, a drain, and a source;
- and
- a discharge device connected between the drain and a predetermined potential;
- and
- a preconditioning circuit for each flash memory cell, comprising:
- a global bitline coupleable to a local bitline of the memory cell;
- a pass transistor through which the global bitline is coupleable to the local bitline;
- and
- a discharge circuit connected between the pass transistor and the local bitline.
7 more elements
Dependencies are inferred from the claim text.