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US 7,120,046 B1Granted
Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
Estimating the term…
Abstract
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.
Claims23
A memory access array comprising:
- a semiconductive substrate;
- a plurality of local data/bit lines extending in a first direction and formed in an upper surface of the substrate at a first pitch;
- a plurality of access transistors extending generally upward from the upper surface of the substrate and aligned generally atop a corresponding local data/bit line, wherein the access transistors comprise:
- a pillar extending upward from the upper surface of the substrate and generally aligned atop the corresponding local data/bit line wherein a source region is formed at a lower portion of the pillar so as to be in electrical communication with the corresponding local data/bit line and a drain region is formed at an upper portion of the pillar with a capacitor contact surface defined at an upper surface of the pillar and
- an opposed gate structure engaging the pillar in at least two opposed lateral directions and extending substantially the entire vertical extent of the pillar;
- a plurality of conductive word lines extending in a second direction and formed at a second pitch and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a lateral extent about the corresponding pillar via the surround gate structure and wherein the cell access transistors are arranged in a plurality of columns along the second direction;
- and
- a plurality of global data/bit lines extending in the first direction,
- wherein the access transistors in at least one column are interconnected between corresponding global data/bit lines and local data/bit lines so as to define local data/bit access transistors between the corresponding global data/bit lines and local data/bit lines and such that remaining columns of access transistors define cell access transistors.
6 more elements
A memory array comprising:
- an access array comprising:
- a semiconductive substrate;
- a plurality of local data/bit lines extending generally in a first direction and formed in an upper surface of the substrate at a first pitch;
- a plurality of access transistors extending generally upward from the upper surface of the substrate and aligned generally atop a corresponding data/bit line, wherein the access transistors comprise:
- a pillar extending generally upward from the upper surface of the substrate and generally aligned atop the corresponding data/bit line wherein a source region is formed generally at a lower portion of the pillar so as to be in electrical communication with the corresponding data/bit line and a drain region is formed generally at an upper portion of the pillar with a capacitor contact defined at upper surfaces of the pillars and
- a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar;
- a plurality of conductive word lines extending generally in a second direction and formed at a second pitch and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a lateral extent about the corresponding pillar via the surround gate structure and wherein the cell access transistors are arranged in a plurality of columns generally along the second direction;
- and
- a plurality of global data/bit lines extending generally in the first direction,
- wherein the access transistors in at least one column are interconnected between corresponding global data/bit lines and local data/bit lines so as to define local data/bit access transistors between the corresponding global data/bit lines and local data/bit lines and such that remaining columns of access transistors define cell access transistors;
- and
- local data/bit access lines in contact with the local data/bit access transistors such that appropriate potential can be applied to the local data/bit access transistors so as to turn on the local data/bit access transistors to provide conduction channels between the local data/bit lines and the global data/bit lines;
- and
- a plurality of storage capacitors interconnected via the capacitor contacts with corresponding cell access transistors so as to define memory cells in combination therewith.
11 more elements
A memory device comprising:
- a substrate;
- a plurality of gate structures having a first and a second end formed on the substrate so as to extend upwards therefrom;
- a plurality of charge storage devices formed adjacent the second end of the plurality of gate structures so as to be electrically connected to a first set of the plurality of gate structures such that the plurality of gate structures and plurality of charge storage devices define an array of memory cells;
- a first set of access conductors formed in the substrate so as to electrically couple to the first set of the plurality of gate structures to thereby allow data to be transferred to and from the memory cells;
- a second set of access conductors formed adjacent the plurality of gate structures such that the second set of access conductors activate the gate structures to allow for conduction between the first and second ends of the gate structures;
- and
- a third set of access conductors formed adjacent the second ends of the plurality of gate structures, wherein the third set of access conductors are coupled to exposed second ends of a second set of the plurality of gate structures such that activation of the second set of gate structures results in a conductive path between the first set of access conductors and the third set of access conductor wherein data can be stored or read in one or more of the memory cells via the first set of access conductors, across the second set of gate structures and then to the third set of access conductors.
4 more elements
Dependencies are inferred from the claim text.