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US 7,120,042 B2Granted
Ferroelectric memory device having test memory cell
AssigneeOki Electric Industry Co., Ltd.
InventorKazuhiko Takahashi
Life of this patent
Estimating the term…
Abstract
A ferroelectric memory device includes a bit line pair, a plurality of memory cells which include one transistor and one ferroelectric capacitor, and a plurality of judgement memory cells which include two transistors and two ferroelectric capacitors. Each of the memory cells is connected to one of the bit lines of the bit line pair, and each of the judgement memory cells is connected to both of the bit lines of the bit line pair.
Claims12
A ferroelectric memory device, comprising:
- a first bit line;
- a second bit line;
- a plurality of first memory cells each of which is connected to the first bit line, wherein each of the first memory cells includes one transistor and one ferroelectric capacitor;
- a plurality of second memory cells each of which is connected to the second bit line, wherein each of the second memory cells includes one transistor and one ferroelectric capacitor;
- a plurality of word lines each of which is connected to a respective one of the first and second memory cells;
- a plurality of plate lines each of which is commonly connected to respective pairs of the first and second memory cells;
- a plurality of judgement memory cells each of which is connected between the first bit line and the second bit line, wherein each of the judgement memory cells includes two transistors and two ferroelectric capacitors;
- and
- a plurality of judgement word line pairs each of which is connected to a respective one of the judgement memory cells, and wherein the judgement word lines of a respective ijudgement word line pair are supplied with a common voltage level.
6 more elements
A ferroelectric memory device, comprising:
- a memory cell array which includes a plurality of first ferroelectric memory cells, wherein each first ferroelectric memory cell has a structure of one transistor and one capacitor;
- a judgement memory cell array which includes a plurality of second ferroelectric memory cells, wherein each second ferroelectric memory cell has a structure of two transistors and two capacitors;
- a pair of bit lines;
- and
- a plurality of judgement word line pairs, each of the judgement word line pairs being connected to respective ones of the second ferroelectric memory cells, wherein judgement word lines of a respective judgement word line pair are supplied with a same voltage level.
- wherein the first ferroelectric memory cells in the memory cell array are alternatively connected to different bit lines of the bit line pair, and wherein the second ferroelectric memory cells in the judgement memory cell array are each connected to both bit lines of the bit line pair.
3 more elements
A ferroelectric memory comprising:
- a memory cell array coupled to a bit line pair and including a plurality of memory cells, each of the memory cells having one transistor and one ferroelectric capacitor;
- a judgement memory cell array coupled to the bit line pair and including a plurality of judgement memory cells, each of the judgement memory cells having first and second transistors and first and second ferroelectric capacitors;
- and
- a plurality of judgement word line pairs, the judgement word line pairs being connected to respectively different ones of the judgement memory cells, and judgement word lines of respective judgement word line pairs are connected together.
1 more element
Dependencies are inferred from the claim text.