Off-chip LC circuit for lowest ground and VDD impedance for power amplifier
AssigneeBroadcom Corporation
InventorsJesus Alfonso Castaneda, Qiang (Tom) Li
Life of this patent
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Abstract
Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface may be made such that the ground and VDD potential levels are effectively brought onto the die of the chip such that a true ground potential is maintained within the chip. This off-chip LC circuit operates cooperatively with an on-chip decoupling capacitor to reduce the overall effective inductance of the bond wires employed to bring signal and voltage levels from the die to the chip exterior. This circuit ensures a relatively low impedance for a PA (Power Amplifier) that is implemented within chip thereby providing for improved performance.
Claims20
An off-chip LC (inductance-capacitance) circuit that communicatively couples to an integrated circuit, the circuit comprising:
- a first RF (Radio Frequency) choke that communicatively couples an off-chip supply potential node to a first pin of the integrated circuit;
- wherein the first pin connects to an on-chip supply potential node of a die that is implemented within the integrated circuit;
- wherein the on-chip supply potential node powers an on-chip PA (Power Amplifier) that is implemented within the die;
- a second RF choke that communicatively couples an off-chip ground potential node to a second pin of the integrated circuit;
- wherein the second pin connects to an on-chip ground potential node of the die;
- wherein the on-chip ground potential node serves as an on-chip ground reference of the on-chip PA;
- an off-chip joining capacitor whose ends communicatively couple to each of the first pin and the second pin of the integrated circuit;
- and
- an off-chip tuning capacitor whose ends communicatively couple to the first pin of the integrated circuit and an off-chip true ground potential node.
An off-chip LC (inductance-capacitance) circuit that communicatively couples to an integrated circuit, the circuit comprising:
- a first RF (Radio Frequency) choke that communicatively couples an off-chip supply potential node to a first pin of the integrated circuit;
- wherein the first pin connects to an on-chip supply potential node of a die that is implemented within the integrated circuit;
- wherein the on-chip supply potential node powers an on-chip PA (Power Amplifier) that is implemented within the die;
- a second RF choke that communicatively couples an off-chip ground potential node to a second pin of the integrated circuit;
- wherein the second pin connects to an on-chip ground potential node of the die;
- wherein the on-chip ground potential node serves as an on-chip ground reference of the on-chip PA;
- an off-chip joining capacitor whose ends communicatively couple to each of the first pin and the second pin of the integrated circuit;
- an off-chip tuning capacitor whose ends communicatively couple to the first pin of the integrated circuit and an off-chip true ground potential node;
- wherein the integrated circuit includes an on-chip decoupling capacitor whose ends communicatively couple to the on-chip supply potential node and the on-chip ground potential node;
- wherein the first pin connects to the on-chip supply potential node of the die via a first bond wire;
- wherein the second pin connects to the on-chip ground potential node of the die via a second bond wire;
- a third pin of the integrated circuit connects to an output of the on-chip PA via a third bond wire;
- a first interface from an exterior of the integrated circuit to the die of the integrated circuit that includes the first pin and the first bond wire is characterized by a first PBWM (Package Bond Wire Model) having a first impedance;
- a second interface from the exterior of the integrated circuit to the die of the integrated circuit that includes the second pin and the second bond wire is characterized by a second PBWM having a second impedance;
- and
- a third interface from the exterior of the integrated circuit to the die of the integrated circuit that includes the third pin and the third bond wire is characterized by a third PBWM having a third impedance.
A method for providing a lowest ground potential and an off-chip supply potential impedance to an on-chip PA (Power Amplifier), the method comprising:
- providing an off-chip joining capacitor and an on-chip decoupling capacitor to reduce an overall effective inductance of a parallel combination of a first PBWM (Package Bond Wire Model) and a second PBWM;
- wherein the first PBWM characterizes a first interface from an exterior of an integrated circuit to a die of the integrated circuit that includes a first pin and a first bond wire;
- wherein the second PBWM characterizes a second interface from the exterior of the integrated circuit to the die of the integrated circuit that includes a second pin and a second bond wire;
- providing an off-chip tuning capacitor to provide a shunt path to dissipate any AC (Alternating Current) signal existent at either of the first pin or the second pin;
- providing a first RF (Radio Frequency) choke to operate as a short circuit with respect to any DC (Direct Current) signal being transmitted between an off-chip supply potential node and the first pin that is communicatively coupled thereto via the first RF choke;
- and
- providing a second RF choke to operate as a short circuit with respect to any DC signal being transmitted between an off-chip ground potential node and the second pin that is communicatively coupled thereto via the second RF choke.
Dependencies are inferred from the claim text.