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US 7,119,598 B2Granted
Clock control circuit and method
AssigneeNEC Electronics Corporation
InventorTakanori Saeki
Life of this patent
Estimating the term…
Abstract
A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.
Claims21
A clock controlling circuit comprising:
- a clock propagation path at least one branching to a first forward branch route and a second forward branch route which are direction-reversed on a side spaced apart from the branching and extend as a first return branch route and second return branch route, respectively, said first return branch route and said second return branch route extending along said second forward branch route and said first forward branch route, respectively, in anti-parallel fashion, and
- at least one timing averaging circuit receiving a clock from a first or second position on said first or second forward branch route and a clock from a second or first position on said second or first return branch route, respectively, each for outputting a signal of delay time corresponding to a time obtained by dividing a timing difference between these clocks in two portions, wherein
- said timing averaging circuit is arranged for charging or discharging an internal node based on a first of said two input clocks undergoing transition at an earlier time and for charging or discharging said internal node based on a second of said two input clocks undergoing transition with a delay time from said first of said two input clocks, wherein
- said timing averaging circuit comprises a plurality of switches, wherein
- at least two of said plurality of switches have a substantially equal on-current, wherein said at least two of said plurality of switches are connected across a first power source and said internal node, and wherein
- another of said plurality of switches is connected across said internal node and a second power source.
3 more elements
A clock controlling circuit comprising:
- a clock propagation path at least one branching to a first forward branch route and a second forward branch route which are direction-reversed on a side spaced apart from the branching and extend as a first return branch route and second return branch route, respectively, said first return branch route and said second return branch route extending along said second forward branch route and said first forward branch route, respectively, in anti-parallel fashion, and
- at least one timing averaging circuit receiving a clock from a first or second position on said first or second forward branch route and a clock from a second or first position on said second or first return branch route, respectively, each for outputting a signal of delay time corresponding to a time obtained by dividing a timing difference between these clocks in two portions, wherein
- said timing averaging circuit is arranged for charging or discharging an internal node based on a first of said two input clocks undergoing transition at an earlier time and for charging or discharging said internal node based on a second of said two input clocks undergoing transition with a delay time from said first of said two input clocks, wherein
- said timing averaging circuit comprises:
- first and second switch elements of said plurality of switches connected in parallel across a first power source and said internal node, said first and second switch elements being turned on and off when the first and second inputs are at first and second values, respectively, and
- a third switch element of said plurality of switches connected across said internal node and a second power source, wherein said third switch element receives said first and second inputs and is turned on when said third switch element is at said second value.
3 more elements
A clock controlling circuit comprising:
- a clock signal propagation path comprising:
- a first branch extending from a branch point and reversing direction at a point opposing the branch point thereby providing a first forward branch and a first return branch;
- and
- a second branch extending from said branch point and reversing direction at said point opposing the branch point thereby providing a second forward branch and a second return branch, said first return branch and said second return branch extending along said second forward branch and said first forward branch, respectively;
- and
- a timing averaging circuit receiving a first clock signal from one of a first position and a second position on one of said first and second forward branches, and a second clock signal from the other of said first position and said second position on the other of said first return branch and said second return branch, and outputting a delay time signal corresponding to a time obtained by dividing a timing difference between the first and second clock signals,
- wherein said timing averaging circuit charges or discharges an internal node based on said first clock signal undergoing transition at an earlier time and that charges or discharges said internal node based on said second clock signal undergoing transition with a delay time from said first clock signal, wherein
- said timing averaging circuit comprises a plurality of switches, wherein
- at least two of said plurality of switches have a substantially equal on-current, wherein said at least two of said plurality of switches are connected across a first power source and said internal node, and wherein
- another of said plurality of switches is connected across said internal node and a second power source.
7 more elements
A clock controlling circuit comprising:
- a clock signal propagation path comprising:
- a first branch extending from a branch point and reversing direction at a point opposing the branch point thereby providing a first forward branch and a first return branch;
- and
- a second branch extending from said branch point and reversing direction at said point opposing the branch point thereby providing a second forward branch and a second return branch, said first return branch and said second return branch extending along said second forward branch and said first forward branch, respectively;
- and
- a timing averaging circuit receiving a first clock signal from one of a first position and a second position on one of said first and second forward branches, and a second clock signal from the other of said first position and said second position on the other of said first return branch and said second return branch, and outputting a delay time signal corresponding to a time obtained by dividing a timing difference between the first and second clock signals,
- wherein said timing averaging circuit charges or discharges an internal node based on said first clock signal undergoing transition at an earlier time and that charges or discharges said internal node based on said second clock signal undergoing transition with a delay time from said first clock signal, wherein
- said timing averaging circuit comprises:
- first and second switch elements of said plurality of switches connected in parallel across a first power source and said internal node, said first and second switch elements being turned on and off when the first and second inputs are at first and second values, respectively, and
- a third switch element of said plurality of switches connected across said internal node and a second power source, wherein said third switch element receives said first and second inputs and is turned on when said third switch element is at said second value.
7 more elements
Dependencies are inferred from the claim text.