Wide-range programmable delay line
AssigneeLSI Logic Corporation
InventorsCheng-Gang Kong, Victor Suen
Life of this patent
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Abstract
An apparatus comprising an input section, a first delay circuit and a second delay circuit. The input section may be configured to present a first intermediate signal by selecting either (i) an input clock signal or (ii) a feedback of an output signal. The first delay circuit may be configured to generate a second intermediate signal by delaying the first intermediate signal by inserting one of a plurality of fixed delays in response to a first control signal. The second delay circuit may be configured to generate the output signal by delaying the second intermediate signal by inserting a programmable delay in response to a second control signal.
Claims20
An apparatus comprising:
- an input section configured to present a first intermediate signal by selecting (i) an input clock signal when said apparatus is in input mode and (ii) a feedback of an output signal when said apparatus is in a feedback mode;
- a first delay circuit configured to generate a second intermediate signal by delaying said first intermediate signal by inserting a first delay comprising one or more fixed increments in response to a first control signal, wherein each of said fixed increments provides a fixed and equal delay;
- and
- a second delay circuit configured to generate said output signal by delaying said second intermediate signal by inserting a second delay in response to a second control signal, wherein said second delay is programmable and different than said fixed increments.
An apparatus comprising:
- means for presenting a first intermediate signal by selecting (i) an input clock signal when said apparatus is in an input mode and (ii) a feedback of an output signal when said apparatus is in a feedback mode;
- means for generating a second intermediate signal by delaying said first intermediate signal by inserting a fixed delay comprising one or more fixed increments in response to a first control signal, wherein each of said fixed increments provides a fixed and equal delay;
- and
- means for generating said output signal by delaying said second intermediate signal by inserting a second delay in response to a second control signal, wherein said second delay is programmable and different than said fixed increments.
A method for implementing a programmable delay comprising the steps of:
- (A) presenting a first intermediate signal by selecting (i) an input clock signal when in an input mode and (ii) a feedback of an output signal when in a feedback mode;
- (B) generating a second intermediate signal with a first delay circuit by delaying said first intermediate signal by inserting a first delay comprising one or more fixed increments in response to a first control signal, wherein each of said fixed increments provides a fixed and equal delay;
- and
- (C) generating said output signal with a second delay circuit by delaying said second intermediate signal by inserting a programmable delay in response to a second control signal, wherein said second delay is programmable and different than said fixed increments.
Dependencies are inferred from the claim text.