Delayed signal generation circuits and methods
AssigneeInternational Business Machines Corporation
InventorsKevin C. Gower, Swati Sathaye
Life of this patent
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Abstract
Circuitry for delaying a signal includes a phase-locked loop comprising one or more output nodes for outputting one or more output signals in response to a reference signal. A buffer is coupled to the output nodes of the phase-locked loop for receiving phase-locked loop output signals and outputs one or more buffered output signals. A multiplexing element receives the buffered output signals and a control signal and generates an operative buffered output signal in response to the control signal. A delay line receives a delay control input signal and the operative buffered output signal from the multiplexing element. The delay line outputs a delayed output signal in response to the delay control input signal.
Claims10
Circuitry for delaying a signal, comprising:
- a phase-locked loop comprising a plurality of separate output nodes for outputting a plurality of separate phase-locked loop output signals in response to a reference signal;
- a plurality of separate buffers coupled to the separate output nodes of the phase-locked loop for receiving separate phase-locked loop output signals, and comprising a plurality of separate output nodes for outputting separate buffered output signals on separate paths;
- a multiplexing element for receiving the separate buffered output signals on the separate path and a control signal, wherein the multiplexing element selects one of the separate buffered output signals on the separate paths as an operative buffered output signal in response to the control signal;
- and
- a delay line receiving a delay control input signal and the operative buffered output signal from the multiplexing element;
- wherein the delay line outputs a delayed output signal in response to the delay control input signal, wherein the delay line includes a plurality of delay elements, wherein the delay control input signal selects a combination of delay elements to define a delay independent from delay in the phase-locked loop.
Circuitry for delaying a signal, comprising:
- a phase-locked loop comprising a plurality of separate more output nodes for outputting a plurality of separate phase-locked loop output signals in response to a reference signal;
- a plurality of separate buffers coupled to the output nodes of the phase-locked loop for receiving separate phase-locked loop output signals, and comprising a plurality of separate output nodes for outputting separate buffered output signals on separate paths;
- and
- a delay assembly further comprising:
- a multiplexing element for receiving the separate buffered output signals on the separate paths and a control signal, wherein the multiplexing element selects one of the separate buffered output signals on the separate paths as an operative buffered output signal in response to the control signal;
- a delay line for receiving a delay control input signal and the operative buffered output signal from the multiplexing element;
- wherein the delay line outputs a delayed output signal in response to the delay control input signal, wherein the delay line includes a plurality of delay elements, wherein the delay control input signal selects a combination of delay elements to define a delay independent from delay in the phase-locked loop;
- and
- a buffer element coupled to the delay line for receiving the delayed output signal.
Dependencies are inferred from the claim text.