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US 7,119,592 B2Granted
Delay locked loop circuit with time delay quantifier and control
AssigneeMicron Technology, Inc.
InventorChris Cooper
Life of this patent
Estimating the term…
Abstract
A delay locked loop circuit has a quantifier for obtaining a measured delay quantity based on a time delay between an external signal and an internal signal. Based on the measured delay quantity, a delay controller controls a correction delay quantity applied to a signal path of the external signal to synchronize the external and internal signals.
Claims45
A memory device comprising:
- a pulse generator including only one output node for generating at the output node a pulse based on a timing relationship between an input signal and a delayed copy of the input signal;
- a quantifier including a plurality of delay elements for propagating the pulse for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input signal and the delayed copy of the input signal.
2 more elements
A memory device comprising:
- a pulse generator for generating a pulse based on a timing relationship between an input signal and a delayed copy of the input signal;
- a quantifier for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input signal and the delayed copy of the input signal, wherein the quantifier includes a plurality of measuring delay elements for propagating the pulse, and wherein the quantifier is configured for selecting the measured delay quantity corresponding to a delay of a group of measuring delay elements of the plurality of measuring delay elements.
2 more elements
A memory device comprising:
- a pulse generator for generating a pulse based on a timing relationship between an input signal and a delayed copy of the input signal;
- a quantifier for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input signal and the delayed copy of the input signal, wherein the pulse generator includes a reset unit for resetting the pulse generator to generate another pulse based on a reset signal.
2 more elements
A memory device comprising:
- a pulse generator for generating a pulse based on an input signal on a signal path and a delayed copy of the input signal on a feedback path;
- a plurality of measuring delay elements for propagating the pulse;
- a quantifying logic unit for quantifying a width of the pulse with the measuring delay elements;
- a control logic circuit for activating a plurality of control signals, each of the control signals representing a different number of measuring delay elements within the plurality of measuring delay elements;
- a plurality of correction delay elements for delaying the input signal to generate a number of delay signals on a number of delay paths coupled to the feedback path;
- and
- a selector responsive to the control signals for selecting one of the delay paths to affect a timing of the delayed copy of the input signal.
4 more elements
A memory device comprising:
- a forward path including plurality of delay elements for applying a correction delay quantity to an input signal to generate an output signal;
- a feedback path for providing a delayed copy of the output signal;
- a pulse generator for generating a pulse based on the input signal and the delayed copy of the output signal;
- a plurality of measuring delay elements for propagating the pulse;
- a plurality of quantifying logic gates for determining a position of the pulse in the measuring delay elements to obtain a measured delay quantity;
- a plurality of storage devices for storing the measured delay quantity;
- and
- a plurality of control logic gates for controlling the correction delay quantity based on the measured delay quantity.
5 more elements
A memory device comprising:
- a memory array;
- a path for transferring data between the memory array cells and data lines;
- and
- a delay locked loop circuit for generating an output signal based on an input signal to control a transfer of the data on the path, the delay locked loop circuit including:
- a pulse generator including only one output node for generating at the output node a pulse based on a timing relationship between the input and output signals;
- a quantifier including a plurality of delay elements for propagating the pulse for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input and output signals.
6 more elements
A memory device comprising:
- a memory array;
- a path for transferring data between the memory array cells and data lines;
- and
- a delay locked loop circuit for generating an output signal based on an input signal to control a transfer of the data on the path, the delay locked loop circuit including:
- a pulse generator for generating a pulse based on a timing relationship between the input and output signals;
- a quantifier for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input and output signals, wherein the quantifier includes:
- a plurality of measuring delay elements for propagating the pulse;
- and
- a quantifying logic unit for quantifying the measured delay quantity with a group of measuring delay elements of the plurality of measuring delay elements.
9 more elements
A memory device comprising:
- a memory array;
- a path for transferring data between the memory array cells and data lines;
- and
- a delay locked loop circuit for generating an output signal based on an input signal to control a transfer of the data on the path, the delay locked loop circuit including:
- a pulse generator for generating a pulse based on a timing relationship between the input and output signals;
- a quantifier for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input and output signals, wherein the pulse generator includes a reset unit for resetting the pulse generator to generate another pulse based on a reset signal.
6 more elements
A memory device comprising:
- a memory array;
- a path for transferring data between the memory array cells and data lines;
- and
- a delay locked loop circuit for generating an output signal based on an input signal to control a transfer of the data on the path, the delay locked loop circuit including:
- a pulse generator including only one output node for generating at the output node a pulse based on a timing relationship between the input and output signals;
- a quantifier for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input and output signals, wherein the delay unit includes an initial delay selector responsive to a selection of the delay controller for delaying the input signal with a minimum delay of the delay unit.
6 more elements
A system comprising:
- a processor;
- and
- a dynamic random access memory device connected to the processor, the dynamic random access memory device including:
- a pulse generator including only one output node for generating at the output node a pulse based on a timing relationship between an input signal and an output signal;
- a quantifier including a plurality of delay elements for propagating the pulse for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input and output signals.
5 more elements
A system comprising:
- a processor;
- and
- a dynamic random access memory device connected to the processor, the dynamic random access memory device including:
- a pulse generator for generating a pulse based on a timing relationship between an input signal and an output signal;
- a quantifier for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input and output signals, wherein the quantifier includes:
- a plurality of measuring delay elements for propagating the pulse;
- and
- a quantifying logic unit for quantifying the measured delay quantity with a group of measuring delay elements of the plurality of measuring delay elements.
8 more elements
A system comprising:
- a processor;
- and
- a dynamic random access memory device connected to the processor, the dynamic random access memory device including:
- a pulse generator for generating a pulse based on a timing relationship between an input signal and an output signal;
- a quantifier for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input and output signals, wherein the pulse generator includes a reset unit for resetting the pulse generator to generate another pulse based on a reset signal.
5 more elements
A system comprising:
- a processor;
- and
- a dynamic random access memory device connected to the processor, the dynamic random access memory device including:
- a pulse generator including only one output node for generating at the output node a pulse based on a timing relationship between an input signal and an output signal;
- a quantifier for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input and output signals, wherein the delay unit includes an initial delay selector responsive to a selection of the delay controller for delaying the input signal with a minimum delay of the delay unit.
5 more elements
A method comprising:
- generating a pulse corresponding to a timing relationship between an input signal and a delayed copy of the input signal;
- propagating the pulse through a number of measuring delay elements to produce different delay pulses at output nodes of the measuring delay elements;
- comparing each of the different delay pulses with the pulse to obtain a measured delay quantity;
- delaying the input signal with a correction delay quantity;
- and
- controlling the correction delay quantity based on the measured delay quantity to adjust the timing relationship between the input signal and the delayed copy of the input signal.
3 more elements
A method comprising:
- generating a pulse based on a timing relationship between an input signal and a delayed copy of the input signal;
- propagating the pulse through a plurality of delay elements for selecting a measured delay quantity corresponding to a width of the pulse;
- selecting a correction delay quantity based on the measured delay quantity;
- and
- delaying the input signal with the correction delay quantity to adjust a timing relationship between the input signal and the delayed copy of the input signal.
2 more elements
A method comprising:
- generating a pulse based on a timing relationship between an input signal and a delayed copy of the input signal;
- selecting a measured delay quantity corresponding to a width of the pulse;
- selecting a correction delay quantity based on the measured delay quantity;
- and
- delaying the input signal with the correction delay quantity to adjust a timing relationship between the input signal and the delayed copy of the input signal, wherein selecting the measured delay quantity includes propagating the pulse through a plurality of measuring delay elements, and wherein the measured delay quantity corresponds to a delay of a group of measuring delay elements of the plurality of measuring delay elements.
2 more elements
A method comprising:
- generating a pulse based on a timing relationship between an input signal and a delayed copy of the input signal;
- selecting a measured delay quantity corresponding to a width of the pulse;
- selecting a correction delay quantity based on the measured delay quantity;
- delaying the input signal with the correction delay quantity to adjust a timing relationship between the input signal and the delayed copy of the input signal;
- and
- generating a second pulse when a reset signal is activated.
3 more elements
A method comprising:
- generating a pulse based on a timing relationship between an input signal and a delayed copy of the input signal;
- selecting a measured delay quantity corresponding to a width of the pulse;
- selecting a correction delay quantity based on the measured delay quantity;
- and
- delaying the input signal with the correction delay quantity to adjust a timing relationship between the input signal and the delayed copy of the input signal, wherein selecting the correction delay quantity includes selecting the correction delay quantity with a minimum delay before the pulse is generated.
2 more elements
A method comprising:
- applying a correction delay quantity to an input signal on a forward path to generate an output signal;
- delaying the output signal on a feedback path to generate a delayed copy of the output signal;
- generating a pulse based on the input signal and the delayed copy of the output signal;
- propagating the pulse through a plurality of measuring delay elements;
- determining a position of the pulse in the measuring delay elements to obtain a measured delay quantity;
- storing the measured delay quantity;
- and
- controlling the correction delay quantity based on the measured delay quantity to adjust a timing relationship between the input signal and output signal.
5 more elements
A memory device comprising:
- a pulse generator including only one output node for generating at the output node a pulse based on a timing relationship between an input signal and a delayed copy of the input signal;
- a quantifier for selecting a measured delay quantity corresponding to a width of the pulse;
- a delay controller for selecting a correction delay quantity based on the measured delay quantity;
- and
- a delay unit for delaying the input signal with the correction delay quantity to adjust a timing relationship between the input signal and the delayed copy of the input signal, wherein the delay unit includes an initial delay selector responsive to a selection of the delay controller for delaying the input signal with a minimum delay of the delay unit before the pulse is generated.
2 more elements
Dependencies are inferred from the claim text.