Delay-locked loop (DLL) integrated circuits having binary-weighted delay chain units with built-in phase comparators that support efficient phase locking

A delay-locked loop integrated circuit, comprising:

• a delay chain configured to generate a multi-bit delay value signal in response to a reference clock signal;
• and
• a delay chain control circuit electrically coupled to said delay chain, said delay chain control circuit comprising a plurality of clock generators responsive to the reference clock signal and a system clock selector configured to generate an internal clock signal received by said delay chain control circuit in response to a plurality of clock signals generated at outputs of the plurality of clock generators and the multi-bit delay value signal.

A delay-locked loop integrated circuit, comprising:

• a delay chain configured to generate a multi-bit delay value signal in response to a reference clock signal;
• and
• a delay chain control circuit responsive to the reference clock signal and the multi-bit delay value signal, said delay chain control circuit configured to generate an internal clock signal having a period that is a function of a value of the multi-bit delay value signal.

A method of operating a locked loop integrated circuit, comprising the steps of:

• evaluating a plurality of binary-weighted delays provided by a corresponding plurality of delay chain units within a delay chain responsive to a reference clock signal, to thereby identify a first one of the plurality of delay chain units having a first delay in excess of a fraction of a period of the reference clock signal;
• and
• removing a second one of the plurality of delay chain units having a second delay in excess of the first delay from a delay path of the delay chain, in response to identifying the first one of the plurality of delay chain units as having the first delay.

A method of operating a locked loop integrated circuit, comprising the steps of:

• generating a multi-bit signal that identifies a plurality of delay chain units within a binary-weighted digital delay line that provide a delay greater than one-half a period of a reference clock signal received at an input of the digital delay line;
• and
• setting a delay of the binary-weighted digital delay line to substantially match a delay of a smallest one of the identified plurality of delay chain units.