Scalable integrated circuit architecture
AssigneeMarvell International Ltd.
InventorYonghua Song
Life of this patent
Estimating the term…
Abstract
An integrated circuit architecture comprises a phase lock loop (PLL) circuit that includes a feedback circuit that receives a reference signal. A voltage controlled oscillator (VCO) generates an output signal to an input of the feedback circuit. A master transistor has a control terminal, a first terminal, and a second terminal that communicates with the VCO. The feedback circuit compares the output signal of the VCO to the reference signal and outputs a drive signal to the control terminal of the master transistor based on the comparison. N slave transistors have control terminals that communicate with the control terminal of the master transistor, first terminals, and second terminals that communicate with respective ones of N circuits.
Claims28
An integrated circuit architecture, comprising:
- a phase lock loop (PLL) circuit that includes:
- a feedback circuit that receives a reference signal;
- a voltage controlled oscillator (VCO) that generates an output signal to an input of said feedback circuit;
- and
- a master transistor having a control terminal, a first terminal, and a second terminal that communicates with said VCO, wherein said feedback circuit compares said output signal of said VCO to said reference signal and outputs a drive signal to said control terminal of said master transistor based on said comparison;
- N circuits;
- and
- N slave transistors having control terminals that communicate with said control terminal of said master transistor, first terminals, and second terminals that communicate with respective ones of said N circuits.
An integrated circuit architecture, comprising:
- phase lock loop (PLL) means for locking onto a reference phase and that includes:
- feedback means for receiving said reference signal;
- voltage controlled oscillator (VCO) means for generating an output signal having a second phase, wherein said feedback means receives said output signal;
- and
- a master transistor having a control terminal, a first terminal, and a second terminal that communicates with said VCO means, wherein said feedback means compares said output signal of said VCO means to said reference frequency and outputs a drive signal to said control terminal of said master transistor based on said comparison;
- N circuits;
- and
- N slave transistors having control terminals that communicate with said control terminal of said master transistor, first terminals, and second terminals that communicate with respective ones of said N circuits.
A method for controlling a bias voltage of N circuits in an integrated circuit, comprising:
- receiving a reference signal having a first phase;
- generating a second signal having a second phase using a voltage controlled oscillator (VCO);
- comparing said first phase to said second phase and generating a drive signal based on said comparison;
- outputting said drive signal to a control terminal of a master transistor;
- coupling a second terminal of said master transistor to said VCO;
- coupling control terminals of N slave transistors to said control terminal of said master transistor;
- and
- coupling second terminals of said N slave transistors to respective ones of said N circuits.
Dependencies are inferred from the claim text.