Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof
AssigneeMediatek Incorporation
InventorJui-Hsing Tseng
Life of this patent
Estimating the term…
Abstract
A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to generate a frequency-divided clock, a programmable delay circuit electrically coupled to the clock divider for delaying the frequency-divided clock to generate the delayed clock, a 180° phase detector electrically coupled to the programmable delay circuit for detecting a phase change of the delayed clock, and a delay lock loop controller electrically coupled to the programmable delay circuit and the 180° phase detector for programming the programmable delay circuit to lock the delayed clock according to the phase change.
Claims14
A delay lock loop circuit for delaying a reference clock to lock a delayed clock, the delay lock loop circuit comprising:
- a clock divider for dividing a frequency of the reference clock by N to generate a frequency-divided clock;
- a programmable delay circuit electrically coupled to the clock divider, the programmable delay circuit for delaying the frequency-divided clock to generate the delayed clock;
- a 180° phase detector electrically coupled to the programmable delay circuit, the 180° phase detector for detecting a phase change of the delayed clock;
- a multiplexer electrically coupled to the clock divider and the reference clock for sending either the reference clock or the frequency-divided clock as a driving clock to the 180° phase detector;
- and
- a delay lock loop controller electrically coupled to the programmable delay circuit and the 180° phase detector, the delay lock loop controller for programming the programmable delay circuit to lock the delayed clock according to the phase change.
A method for delaying a reference clock to lock a delayed clock, the method comprising:
- dividing a frequency of a reference clock by N to generate a frequency-divided clock;
- delaying the frequency-divided clock by an amount of delay to generate the delayed clock;
- providing a 180° phase detector, and utilizing the 180° phase detector for detecting a phase change of the delayed clock;
- and
- selecting the reference clock or the frequency-divided clock to be a driving clock of the 180° phase detector,
- programming the amount of delay for locking the delayed clock according to the phase change.
A delay lock loop circuit comprising:
- a clock divider and programmable delay circuit for dividing a frequency of a reference clock by N and delaying the frequency to thereby generate a delayed and frequency-divided clock;
- a 180° phase detector electrically coupled to the clock divider and programmable delay circuit, the 180° phase detector for detecting a phase change of the delayed and frequency-divided clock;
- and
- a delay lock loop controller electrically coupled to the clock divider and programmable delay circuit, and the 180° phase detector;
- the delay lock loop controller for programming the clock divider and programmable delay circuit to lock the delayed and frequency-divided clock according to the phase change.
A method for delaying a reference clock, the method comprising:
- dividing a frequency of a reference clock by N and delaying the frequency by an amount of delay to thereby generate a delayed and frequency-divided clock;
- providing a 180° phase detector, and utilizing the 180° phase detector for detecting a phase change of the delayed and frequency-divided clock;
- and
- programming division of the reference clock and amount of delay for locking the delayed and frequency-divided clock according to the phase change.
Dependencies are inferred from the claim text.