High frequency divider state correction circuit
AssigneeInternational Business Machines Corporation
InventorsDavid William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
Life of this patent
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Abstract
The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted to a third flip flop. In one aspect, the received value transmitted to the third flip flop comprises an unaltered received value. In another aspect, the received value transmitted to the third flip flop comprises transmitting an altered received value. This allows for an incorrect state within the state machine to change to a correct state after a few clock pulses.
Claims15
A frequency divider state circuit, comprising:
- a first flip flop coupled to receive a feedback signal and a clock signal, and configured to produce a first output signal dependent upon the feedback signal and the clock signal;
- a second flip flop coupled to receive the first output signal, the clock signal, and an error signal indicative of an error state, wherein the second flip flop comprises logic coupled to receive the clock signal and the error signal and configured to produce an internal clock signal dependent upon the clock signal and the error signal, and wherein the second flip flop is configured to produce a second output signal dependent upon the first output signal, the clock signal, and the internal clock signal;
- a third flip flop coupled to receive the second output signal and the clock signal, and configured to produce a third output signal dependent upon the second output signal and the clock signal;
- and
- wherein the frequency divider state circuit is configured to produce an output signal having a frequency that is less than a frequency of the clock signal.
A frequency divider state circuit, comprising:
- a first flip flop coupled to receive a first feedback signal and a clock signal, and configured to produce a first output signal and an inverted version of the first output signal dependent upon the feedback signal and the clock signal;
- a second flip flop coupled to receive the first output signal and the clock signal, and configured to produce a second output signal and an inverted version of the second output signal dependent upon the first output signal and the clock signal;
- a correction circuit coupled to receive the inverted versions of the first and second output signals and a second feedback signal, and configured to produce a third output signal dependent upon the inverted versions of the first and second output signals and the second feedback signal;
- a third flip flop coupled to receive the third output signal and the clock signal, and configured to produce a fourth output signal, and an inverted version of the fourth output signal as the second feedback signal, dependent upon the third output signal and the clock signal;
- a fourth flip flop coupled to receive the fourth output signal and the clock signal, and configured to produce a fifth output signal dependent upon the fourth output signal and the clock signal;
- and
- wherein the frequency divider state circuit is configured to produce an output signal having a frequency that is less than a frequency of the clock signal.
Dependencies are inferred from the claim text.