Signal samplers and buffers with enhanced linearity
AssigneeAnalog Devices, Inc.
InventorAhmed Mohamed Abdelatty Ali
Life of this patent
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Abstract
The invention recognizes that sampler linearity is degraded because transfer voltage across a sampler's buffer varies with amplitude of the analog signal being sampled. Because this transfer voltage is in the signal path it modulates the signal and distorts the resulting sample. In the invention, sampler embodiments are provided which include replica current generators that provide and route sample currents to sample capacitors so that an associated buffer transistor can transfer a faithful copy of the analog signal's potential to the sample capacitor and thereby significantly enhance the sampler's linearity. The replica current generators generally include a replica load that mimics the sample load driven by the buffer transistor.
Claims31
An amplifier for impelling current in a signal load in response to an input signal, comprising:
- a buffer transistor having a buffer control terminal and first and second buffer current terminals responsive to said buffer control terminal wherein said first buffer current terminal is available to impel a desired load current in said signal load in response to said input signal at said buffer control terminal;
- a replica current generator that provides a replica current in response to said input signal;
- and
- a current folder that directs said replica current to said first buffer current terminal to thereby supply said load current.
A sampler that provides samples of an analog signal, comprising:
- an upstream buffer transistor for receiving said analog signal;
- a sample capacitor;
- a downstream buffer transistor positioned between said sample capacitor and said upstream buffer transistor to couple a sample of said analog signal to said sample capacitor in a first sampler mode and isolate said sample capacitor from said analog signal in a second sampler mode;
- and
- at least one of an upstream replica current generator and a downstream replica current generator that respectively provide an upstream replica current and a downstream replica current to thereby reduce current variations in a respective one of said upstream and downstream buffer transistors;
- wherein said downstream replica current generator and said downstream buffer transistor respond to opposite polarities of said analog signal;
- wherein said downstream replica current generator includes:
- a replica current source;
- a replica capacitor;
- and
- a replica transistor coupled between said downstream buffer transistor and said replica current source and said replica capacitor;
- wherein said downstream buffer transistor and said replica transistor are arranged as emitter followers to respectively drive said sample capacitor and said replica capacitor;
- and
- wherein said replica transistor receives an opposite polarity of said analog signal through a level shifter to prevent saturation of said replica transistor.
A sampler that provides samples of an analog signal, comprising:
- an upstream buffer transistor for receiving said analog signal;
- a sample capacitor;
- a downstream buffer transistor positioned between said sample capacitor and said upstream buffer transistor to couple a sample of said analog signal to said sample capacitor in a first sampler mode and isolate said sample capacitor from said analog signal in a second sampler mode;
- and
- at least one of an upstream replica current generator and a downstream replica current generator that respectively provide an upstream replica current and a downstream replica current to thereby reduce current variations in a respective one of said upstream and downstream buffer transistors;
- wherein:
- said upstream replica current generator and said upstream buffer transistor respond to opposite polarities of said analog signal;
- and
- said downstream replica current generator provides a replica current to said downstream buffer transistor in response to said upstream replica current generator.
A sampler that provides samples of an analog signal, comprising:
- an upstream buffer transistor for receiving said analog signal;
- a sample capacitor;
- a downstream buffer transistor positioned between said sample capacitor and said upstream buffer transistor to couple a sample of said analog signal to said sample capacitor in a first sampler mode and isolate said sample capacitor from said analog signal in a second sampler mode;
- and
- at least one of an upstream replica current generator and a downstream replica current generator that respectively provide an upstream replica current and a downstream replica current to thereby reduce current variations in a respective one of said upstream and downstream buffer transistors;
- wherein said downstream replica current generator provides a replica current to said downstream buffer transistor in response to said upstream buffer transistor.
A sampler that provides samples of an analog signal, comprising:
- an upstream buffer transistor for receiving said analog signal;
- a sample capacitor;
- a downstream buffer transistor positioned between said sample capacitor and said upstream buffer transistor to couple a sample of said analog signal to said sample capacitor in a first sampler mode and isolate said sample capacitor from said analog signal in a second sampler mode;
- and
- at least one of an upstream replica current generator and a downstream replica current generator that respectively provide an upstream replica current and a downstream replica current to thereby reduce current variations in a respective one of said upstream and downstream buffer transistors;
- wherein said downstream replica current generator includes:
- a downstream replica current source;
- a downstream folding current source;
- a downstream replica capacitor coupled between said downstream replica current source and said downstream folding current source;
- a downstream replica transistor that drives said downstream replica capacitor in response to said analog signal;
- and
- a downstream folding transistor that couples said downstream replica capacitor to said downstream buffer transistor;
- and wherein said upstream replica current generator includes:
- an upstream replica current source;
- an upstream folding current source;
- an upstream replica capacitor coupled to said upstream folding current source;
- an upstream replica transistor that responds to said analog signal;
- an upstream replica buffer transistor that drives said upstream replica capacitor in response to said upstream replica transistor;
- and
- an upstream folding transistor that couples said upstream replica capacitor to said upstream buffer transistor.
A sampler that provides samples of an analog signal, comprising:
- an upstream buffer transistor for receiving said analog signal;
- a sample capacitor;
- a downstream buffer transistor positioned between said sample capacitor and said upstream buffer transistor to couple a sample of said analog signal to said sample capacitor in a first sampler mode and isolate said sample capacitor from said analog signal in a second sampler mode;
- and
- at least one of an upstream replica current generator and a downstream replica current generator that respectively provide an upstream replica current and a downstream replica current to thereby reduce current variations in a respective one of said upstream and downstream buffer transistors;
- wherein said downstream replica current generator includes:
- a downstream replica current source;
- a downstream folding current source;
- a downstream replica capacitor coupled between said downstream replica current source and said downstream folding current source;
- a downstream folding transistor that couples said downstream replica capacitor to said downstream buffer transistor;
- and
- a downstream replica transistor that drives said downstream replica capacitor;
- and wherein said upstream replica current generator includes:
- an upstream replica current source;
- and
- an upstream replica transistor that couples said upstream replica current source to said upstream buffer transistor and responds to an opposite polarity of said analog signal;
- and further including a second upstream replica transistor that drives said downstream replica transistor in response to said analog signal.
Dependencies are inferred from the claim text.