Phase detection in a sync pulse generator
AssigneeHewlett-Packard Development Company, L.P.
InventorRichard W. Adkisson
Life of this patent
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Abstract
A phase detector and phase detection method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The first clock domain is operable with a first clock signal and the second clock domain is operable with a second clock signal. At least one first flip flop is operable to sample the first clock signal with a rising edge of the second clock signal and at least one second flip flop is operable to sample the first clock signal with a falling edge of the second clock signal. The sampling produces transitions indicative of the coincident rising edges between the first and second signals.
Claims27
A phase detector operable with a first clock signal and a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, comprising:
- at least one first flip flop operable to sample said first clock signal with a rising edge of said second clock signal, said at least one first flip flop thereby operating to assert a first sampled clock signal having a zero-to-one transition therein that is indicative of coincident rising edges in said first and second clock signals;
- and
- at least one second flip flop operable to sample said first clock signal with a falling edge of said second clock signal, said at least one second flip flop operating to assert a second sampled clock signal having a one-to-zero transition therein that is indicative of coincident rising edges in said first and second clock signals, wherein said first and second sampled clock signals are operable to be forwarded to validation circuitry for validating said coincident rising edges based upon skew tolerance between said first and second clock signals and to generate a valid edge signal responsive thereto.
A phase detection method operable with a first clock signal and a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, comprising:
- sampling said first clock signal with a rising edge of said second clock signal to assert a first sampled clock signal having a zero-to-one transition therein that is indicative of coincident rising edges in said first and second clock signals;
- sampling said first clock signal with a falling edge of said second clock signal to assert a second sampled clock signal having a one-to-zero transition therein that is indicative of coincident rising edges in said first and second clock signals;
- and
- forwarding at least one of said first and second sampled clock signals indicative of coincident rising edges to validation circuitry, said validation circuitry for validating said coincident rising edges based upon skew tolerance between said first and second clock signals and to generate a valid edge signal responsive thereto.
A phase detection system operable with a first clock signal and a second clock signal having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, comprising:
- means for sampling said first clock signal with a rising edge of said second clock signal to assert a first sampled clock signal having a zero-to-one transition therein that is indicative of coincident rising edges in said first and second clock signals;
- and
- means for sampling said first clock signal with a falling edge of said second clock signal to assert a second sampled clock signal having a one-to-zero transition therein that is indicative of coincident rising edges in said first and second clock signals, wherein at least one of said first and second sampled clock signals indicative of coincident rising edges is operable to be forwarded to validation circuitry, said validation circuitry for validating said coincident rising edges based upon skew tolerance between said first and second clock signals and to generate a valid edge signal responsive thereto.
An apparatus operable with a first clock signal and a second clock signal, comprising:
- at least one first flip flop operable to sample said first clock signal with a rising edge of said second clock signal to generate a first sampled clock signal;
- and
- at least one second flip flop operable to sample said first clock signal with a falling edge of said second clock signal to generate a second sampled clock signal, said sampling by said at least one first and one second flip flops producing transitions in said first and second sampled clock signals indicative of coincident edges between said first and second clock signals, wherein at least one of said first and second sampled clock signals indicative of coincident rising edges is operable to be forwarded to validation circuitry, said validation circuitry for validating said coincident rising edges based upon skew tolerance between said first and second clock signals and to generate a valid edge signal responsive thereto.
Dependencies are inferred from the claim text.